Guidelines improve test quality in advanced CMOS nodes

Executive Summary

As we move towards small-scale CMOS technology nodes, the complexity and functional frequency of the design increases tremendously. With a shrinking channel length of CMOS devices, the probability of physical defects increases. Consequentially, after the 90nm CMOS technology node, it becomes mandatory to insert DFT logic in the design.

DFT (Design For Testability) provides certain techniques to convert the original design to a testable design. With the advancement in the process technology nodes, there are many much improved and efficient DFT technologies which are developed for better tests. The basic goal of the DFT technique is to avoid any possible test escape (false positives) in the design.

Project Highlights

The test escape can cause the erroneous parts to be shipped to the customer along with good parts. The faulty parts may return back during system testing, thus leading to wastage of time, money and resources of the OEMs (Original Equipment Manufacturers) and EMS (Electronic Manufacturing Services) companies. Such types of test escapes can prove to be immensely costly and a hassle to OEMs and EMS companies, so proper test strategies need to be developed to avoid test escapes and improve test quality.
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