Grasping the Low Power Fundamentals

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Grasping-the-Low-Power-Fundamentals

Description

Every market operates on this principle: “ Customer is the king”. Among electronic gadgets, customer expectations are high performance multimedia experience, new and advanced features, smaller product size, low battery consumption and affordable price. And these are just minimum expectations.

For decades, the VLSI industry follows one law to fulfill the customer’s needs , the Moore’s Law. It states that number of transistors per chip would grow exponentially (double very 18 months). It is actually not a law; it is a passionate statement or perhaps a visionary one. Obeying this law led the VLSI industry to exponentially increase chip density. This resulted in language based design and synthesis, and design and IP reuse to approach complex SoC functionality.

Publications

To fulfill these expectations, transistor scaling is the key. However, nano -scale designs at 130nm and below have now reached a power dissipation level beyond the limits of IC packaging and cooling techniques. Even to increase the speed , increasing clock after a limit is also not possible at some technology node.

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    Description

    Every market operates on this principle: “ Customer is the king”. Among electronic gadgets, customer expectations are high performance multimedia experience, new and advanced features, smaller product size, low battery consumption and affordable price. And these are just minimum expectations.

    For decades, the VLSI industry follows one law to fulfill the customer’s needs , the Moore’s Law. It states that number of transistors per chip would grow exponentially (double very 18 months). It is actually not a law; it is a passionate statement or perhaps a visionary one. Obeying this law led the VLSI industry to exponentially increase chip density. This resulted in language based design and synthesis, and design and IP reuse to approach complex SoC functionality.

    To fulfill these expectations, transistor scaling is the key. However, nano -scale designs at 130nm and below have now reached a power dissipation level beyond the limits of IC packaging and cooling techniques. Even to increase the speed , increasing clock after a limit is also not possible at some technology node.

    Publications

    To read more, download the copy

    arrows-new-1

    To download this resource

    Fill in the details below





      I wish to be contacted by eInfochips


      For all career related inquiries, kindly visit our careers page or write to career@einfochips.com

      Fill in the details below





        I wish to be contacted by eInfochips


        For all career related inquiries, kindly visit our careers page or write to career@einfochips.com