SOC (System On Chip) and behavioral designs are integrating more systems and functions to meet market demands for improved user experience. More often than not, these systems and functions require access to of-chip DRAM to support the required increase in compute performance. As not all of the systems access DRAM in the same fashion, with the same traffic pattern, or with he same bandwidth requirement, designers must find the right technique to effectively balance off-chip DRAM access for all of the behavioral designs.

This paper represents a generic executable architecture. It represents the efficient behavior of the Memory Model to be used for verification of SOC communicating with DDR SDRAMs or can be used as the third party Model verification (passive element). Paper shows the capability as standalone VIP architecture and also represents the market value of DDR model in the present technical era with different technical views and challenges faced. It also gives solutions of supporting different part number of established DDR vendors like Micron, Elpidam Samsung etc.