SOC (System On Chip) and behavioral designs are integrating more systems and functions to meet market demands for improved user experience. More often than not, theses systems and functions require access to of-chip DRAM to support the required increase in compute performance. As not all of the systems access DRAM in the same fashion, with the same traffic pattern, or with he same bandwidth requirement, designers must find the right technique to effectively balance off-chip DRAM access for all of the behavioral designs.

Now, SoC is left with limited scope as far as designing of complex chip is concerned, with routing congestion as its main problem. As the number of blocks and IPs on a small area increases, connection between them is now possible. To reduce routing congestion in the SoC environment, network on chip (NoC) comes into picture. It will make designs more reliable and cost effective, as well as render better overall performance.