Boundary scan: Seven benefits

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Boundary scan: Seven benefits

Description

Boundary scan test techniques were first discussed in the late 1980s. At that time, experts believed that the growing complexity of chips would have a serious effect on an ICT system’s ability to place a nail accurately on a test pad. In addition, the development of multi-layer boards compounded the problem of physical access for testing interconnects between devices on a PCB.

Publications

Many of the testing industry experts predicted that the “bed of nails” test system would disappear with the increasing complexity of chips. As a result, a group of concerned test engineers banded together to address this problem. The group was known as the Joint Test Action Group (JTAG). Their preferred solution was to access device pins by means of an internal serial shift register around the boundary of the device as shown below. In the boundary scan design, the chip’s IOs were supplemented with the boundary scan cell (a storage element). The collection of boundary scan cells on a board can be configured in various ways to achieve a parallel-in, parallel-out shift register that is used for testing and for on-board programming purposes.

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    Description

    Boundary scan test techniques were first discussed in the late 1980s. At that time, experts believed that the growing complexity of chips would have a serious effect on an ICT system’s ability to place a nail accurately on a test pad. In addition, the development of multi-layer boards compounded the problem of physical access for testing interconnects between devices on a PCB.

    Many of the testing industry experts predicted that the “bed of nails” test system would disappear with the increasing complexity of chips. As a result, a group of concerned test engineers banded together to address this problem. The group was known as the Joint Test Action Group (JTAG). Their preferred solution was to access device pins by means of an internal serial shift register around the boundary of the device as shown below. In the boundary scan design, the chip’s IOs were supplemented with the boundary scan cell (a storage element). The collection of boundary scan cells on a board can be configured in various ways to achieve a parallel-in, parallel-out shift register that is used for testing and for on-board programming purposes.

    Publications

    To read more, download the copy

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    To download this resource

    Fill in the details below





      I have read and understand the Privacy Policy By submitting this form, I acknowledge that I have read and understand the Privacy Policy

      I wish to be contacted by eInfochips I wish to be contacted by eInfochips

      For all career related inquiries, kindly visit our careers page or write to career@einfochips.com

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        I have read and understand the Privacy Policy By submitting this form, I acknowledge that I have read and understand the Privacy Policy

        I wish to be contacted by eInfochips I wish to be contacted by eInfochips

        For all career related inquiries, kindly visit our careers page or write to career@einfochips.com