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Synthesizing Low Power ASIC for Efficient SoC Design
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Sarvang Sanghavi
February 25, 2026
Sarvang Sanghavi is a Technical Lead (Level 2) in the Physical Design team at eInfochips. Over the past nine years, he has delivered low-power, high-performance layouts on cutting-edge nodes for flagship smartphone chipsets and battery-critical MCU projects. His core strengths include power grid design, multi-voltage domain implementation and verification, advanced IR/EM closure, and sign-off timing optimization. He earned his B.E. in Electronics and Communication Engineering from Vishwakarma Government Engineering College, Ahmedabad.
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