A turnkey RTL‑to‑GDSII execution program was undertaken for a complex, high‑performance networking SoC targeting advanced process nodes. The objective was to significantly improve manufacturing test quality while meeting aggressive schedules and stringent power and performance constraints.
The program addressed critical challenges related to low fault coverage observed in earlier silicon that resulted in defective parts escaping into production. The next-‑generation design required a comprehensive ownership model spanning Design-for-Test (DFT), physical design, timing, and signoff to ensure high test coverage, robust silicon quality, and clean production readiness under tight delivery timelines.
Key Highlights
- Executed full RTL‑to‑GDSII flow for advanced 5nm and 3nm SoCs
- Handled RTL and DFT architecture changes mid‑cycle
- Resolved TDF shift speed issues through ‑cross team DFT and STA collaboration
- Increased tester shift frequency from 80 MHz to 200 MHz without schedule impact
- Implemented scan, ATPG, and pattern validation at block and top levels
- Applied incremental routing and timing signoff for rapid convergence
