Spare Cell Leakage Minimization in Physical Design – Part 1

Executive Summary

Leakage in IC designs constitutes a significant amount of power dissipation because CMOS gates are not ideal switches. The leakage in CMOS gates varies significantly for different combinations of input values, from which “state-dependent gate leakage tables” are derived. This leakage power is dissipated even when the gates are not switching. Traditionally, spare cells remain inactive in the design and thus contribute to leakage power consumption. Here is an approach to minimize the state-dependent leakage power dissipation of the spare cells.
Power minimization has been a major challenge in VLSI designs to get the best performance out of the devices. Principally, ASICs for portable devices like cell phones or wireless devices require special effort to minimize power consumption. Leakage power consumption will plague CMOS gates even when the circuit is in inactive state, as transistors are not perfect switches. In sub nanometer designs, leakage current is dominated by sub-threshold leakage, gate-oxide tunneling leakage and reverse-bias PN junction leakage.
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