Project Statistics |
PROPEXT_xilxSynthMaxFanout_virtex2=100000 |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2014-04-05T11:13:55 |
PROP_intWbtProjectID=8E47CDE824FA08BFEBA5F108DC27ACA9 |
PROP_intWbtProjectIteration=42 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxBitgStart_IntDone=true |
PROP_AutoTop=true |
PROP_CompxlibEdkSimLib=false |
PROP_DevFamily=Spartan3A and Spartan3AN |
PROP_DevDevice=xc3s400an |
PROP_DevFamilyPMName=spartan3a |
PROP_DevPackage=fgg400 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=2 |
FILE_VERILOG=28 |