| EE Times – Year 2010 |
eInfochips ranked top chip design services provider by Gartner |
| CIOL – Year 2012 |
The Powerful, Free Automation Tool – AutoHotKey – By Bhavin Patel |
| TechOnline India – Year 2011 |
FPGA Prototyping – HDL migration and FPGA Debug – By Sachin Gorkhe |
| Electronics Maker – Year 2009 |
Guest column on RFID by Rajeev Kaushal in the article – RTLS: A technology for effective tracking solutions – By D. K. Ramkumar |
| ECN ASIA – Year 2009 |
Boosting data transfer over network with TOE By Niraj Patel. |
| Xilinx Xcell Journal – Year 2009 |
How to Tame the Power Beast in Consumer Hand Held MPU By Rahul V. Shah and Vishesh Agrawal |
| EDN Asia – Year 2009 |
Why outsource designs? |
| From Project to Product Engineering |
| Electronic Design – Year 2009 |
Break Through The TCP/IP Bottleneck With iWARP |
| VARIndia – Year 2009 |
IPTV shows Promise in India but needs QoS Enhancement |
| Wireless Collaboration with .NET by Ashish Shah |
| EDN US – Year 2009 |
Estimating Power in FPGA Design by Rahul V Shah |
| EFY – Year 2009 |
Embedded System Can India Move from Implementing to Initiate Products? |
| Techonlineindia.com – Year 2009 |
Technology development strategy in difficult times by Mr Rajeev Gupta |
| EDA Design line – Year 2009 |
HDL design methods for low-power design by Kaushal Buch |
| A&S International – The leading International Security Magazine – Year 2009 |
Comparing Chipset Platforms: Nuts and Bolts of Video Surveillance |
| EDN Asia – Year 2008 |
eInfochips Announces DDR2 SDRAM Verification IP and Reed Solomon Encoder Design IP |
| Fabless yet Fabulous By Nirav Shah, Director of Marketing, eInfochips |
| EE Times – Year 2008 |
Tools manage verification data report by Rahul V Shah |
| Electronics Maker – Year 2008 |
Software Tools and Developments for Automotive electronics |
| A&S Asia – Year 2008 |
Utility Security Upholds |
| Chip Design Magazine – Year 2008 |
Quantification-Based Verification Checks Embedded – Systems Video Quality by Bhaskar Trivedi |
| Xcell Journal – Year 2008 |
A/V Monitoring System Rides Virtex-5 by Manish Desai (Project Lead – ASIC – FGPA) |
| ECN Asia – Year 2008 |
The five commandments of outsourcing written by Mr Nilesh Ranpura |
| VLSI Society of India’s VSI Journal – Year 2008 |
Performance enhancement in SPI 4.2 IP Core |
| Chip Design – Year 2006 |
System Verilog Community Builds with Verification IP |
| Assertion-Based Verification Shortens Project Design Time By Shailesh Dave |
| Chip Design – Year 2005 |
Navigating the Silicon Jungle: FPGA or ASIC? |
| Latest Challenges & Trends in Chip Verification |
| EETimes – Year 2005 |
Cluster-based approach eases clock tree synthesis By Udhaya Kumar |
| UWB gaining infrastructure By Ron Wilson |
| Electronic Design – Year 2005 |
Simulation Mismatches Can Foul Up Test-Pattern Verification By Udhaya Kumar |
| EDN Asia – Year 2005 |
FPGAs implementing high-end image-processing applications By Pradeep Chakraborty |
| SOC Central : White paper – Year 2005 |
Elements of Verification By Rohit Dubey |
| Express Computers – Year 2005 |
4Gbps to the fore By Venkatesh Ganesh |
| EE Times – Year 2004 |
When requirements outrun an architecture By Ron Wilson |
| Digital ‘verification IP’ is becoming more design-like By Ron Wilson |
| Getting an algorithm ready for reuse By Ketul Patel |
| Embedded test tackles verification times By Nicolas Mokhoff |
| Inside a hybrid verification model By Nilesh Ranpura |
| IP model shift: from blocks to app-specific subsystems By Ron Wilson |
| Outsourcing backers say move up food chain, foes question new job claims |
