Posts by Smit Patel

Smit Patel is working as an Engineer at eInfochips, an Arrow company. He has an experience of almost 3 years in ASIC Design Verification and has worked on ATE domain verification projects. He also has a hands-on experience in Functional and SVA-based verification.

System Verilog Assertions Simplified


Assertion is a very powerful feature of System Verilog HVL