The DSP Controller core verification activity involves development of various driver-monitor and checker to verify DSP controller core , it consists of advanced DSP processor with modem control interface to connect it to external analog section of modem control application. The controller also has APB interface to communicate it with host CPU. The advanced JTAG debugger support is provided for testing and verification.

eInfochips’ Role:

eInfochips' role was to perform in-depth qualitative verification of the DSP Controller that covered following major attributes

• To define a simulation driver monitor implementation and test Plan
• To implement Driver, Checker and Monitor for 7 sub-modules of DSP controller core
• To Perform verification on Driver-Monitor and checker for all 7 sub-modules

How was this achieved?

• Understanding the functionality of current code simulation monitors in VHDL/C
• Defining implementation specs for monitors-drivers on Verilog platform
• JTAG/HDS interface verification plan covering memory upload/download, breakpoint, and single step and trace execution type of functions
• Simulation Driver-Monitor was implemented in Verilog based on the implementation plan and as per the given functionality defined by Client in VHDL/C code, using test-bench supplied by the Client
• Using the implementation plan and environment, above models were verified against functionality of VHDL/C models
• Correct and consistent behavior was checked on the DSP core with reference to available VHDL and C code functionalities
• Verified the DUT/BFM using available test cases from Client on this implemented environment and compared their validity against the available reference