Our customer is a global leader in semiconductors for storage, wireless data, and public and enterprise networks. The project involved development of a full custom macro using TSMC 90nm technology. The goal was to develop high speed, low power viterbi decoder macro using the minimum die area within 6 months.

eInfochips’ Role:

eInfochips' layout engineers were responsible for generating the DRC/LVS/DFM clean layout of their full custom design based on the schematics available from their design team. The height of the leaf cells and standard cells were decided by various cell height experiments to get the best density ratio. Once the cell height was determined, the leaf cells and the standard cells were developed considering the critical timing paths. Manual routing was done at the leaf level cells to get the compact design. After creating the block level modules and the top module, transistor level timing analysis was done. eInfochips was responsible for generation of layout of branch matrix unit, Add-compare-select unit and the trellis block.

At various stages the eInfochips role was

• To determine the cell height for the standard cells with optimum density
• To create leaf cell layouts from the given schematic using 90nm TSMC technology rules
• Floorplanning and Routing of the block and top level module
• To run Synopsys Hercules DRC rule-deck and make the Layout DRC clean
• Run ASSURA LVS and make the design LVS clean
• Run transistor level timing analysis and provide feedback to the customer regarding the design performance

Tools Used

• Cadence Virtuoso custom design platform (Virtuoso-XL Layout editor and Assura for checking LVS )
• Synopsys Hercules tool for DRC and DFM sign-off verification.
• Synopsys Pathmill for the transistor level timing analysis.

How was this achieved?

eInfochips achieved the task with one project leader and two layout engineers for duration of 6 months. The total effort was 12 man-months.