eInfochips’ FPGA design methodology encompasses a simulation and verification based approach. We en-arm our RTL designs with bus functional models, embedded processor models and RTL test suites to provide a comprehensive system test environment.

Our FPGA methodology is robust and capable of handling designs of any complexity owing to years of evolution. As a services organization, eInfochips can easily adapt to clients methodologies with expertise in both VHDL and Verilog. Our comprehensive service spectrum across varous silicon phases is listed below:

Pre-Silicon Validation:

• Hardware Acceleration
  • EVE, Palladium
  • Synthesizable Transactors
    
• Hardware Software Co-verification
  
• FPGA Prototyping
  
• Pre-prototype Firmware Development & Test

Chip Bring-up and Post-Silicon Validation:

• Chip bring-up & Characterization
  
• Board level Silicon Validation
  
• Firmware Development & Testing
  

System Validation:

• Silicon & Board Functionality Validation
• System-level Validation with Application
  
• SI, Environmental, Thermal and EMI Testing
  
• Reliability and Stress Testing

Expertise:

ASIC Prototyping on FPGA

eInfochips helps customers prototype their ASIC designs on FPGAs before committing to ASICs. Our association with the client would start at the system architecture level in defining FPGA prototype functionality, clock speeds, data rates etc. which could be realistically achieved.

This service typically includes:

• Modification / optimization of the ASIC RTL for FPGA
• Implementation
  
• Test bench tuning
  
• Verification & equivalence checking
  
• Design Partitioning onto multiple FPGAs if required
  
• Floor planning
  
• Place and route

The service also includes development of an evaluation board around the FPGAs or in some cases development of an off-the-shelf FPGA prototyping board.