With over 14 years in existence, close to 2500 man-years experience among 200+ ASIC design & verification engineers and over 145 first pass silicon successes across various industries, einfochips is your right choice for managed Chip/ASIC/SoC design & verification services & solutions.
eInfochips is an early adopter of the latest in chip design and EDA technologies owing to its close partnerships with major EDA companies like Synopsys, Cadence and Mentor Graphics.Our DO-254 (Avionics standards) trained Design Quality Engineers and Process Analysts qualify us to provide flight critical applications ASIC/SoC/FPGA Design & Verification services.
eInfochips’ offshore design centers have delivered multitude silicon solutions to technology companies worldwide through its operational excellence model that enables:
VMM based Verification of DMA Sub-system:
eInfochips offers VMM based turnkey verification of DMA-Sub System (DMA–SS), PCI module and PCIe module; provides 100% functional coverage
analysis
MIPI® CSI-2 VMM based Verification IP:
Based on the layered architecture of object oriented programming that allows coverage driven verification suitable for verifying transmitter and receiver
Chip Tester FPGA module : Design, verification & board bring-up of chip tester equipment module on Xilinx Virtex-5 FPGA
RTL to GDSII for a Networking chip: Services offered include physical layout, post layout, DRC LVS and formal verification using Mentor & Magma tools on 0.09um chartered semiconductor with 9 layers
eInfochips ensures that you meet your scheduled time to market everytime with a first pass-silicon through its efficient and highly evolved execution methodology. We help our customers with a timely delivery of their silicon provided customer queries are responded within 24 hours, all SoW actions are resolved as committed, project plans are updated on a monthly basis.
Zero post-silicon bugs for defined engagement
eInfochips considers every ASIC verification project as an R & D project of product development/verification covering not only design/logic but architecture, software.
With extensive expertise through years of rigorous implementation of most of the verification methodologies including VMM, OVM, eRM, UVM, AVM & RVM, eInfochips has developed a robust and fool-proof verification process to ensure that your silicon passes first time right, all the time.
Not 99.99%... but 100% functional and code coverage
We focus on building well constructed, robust and complete verification environments that cover unit/cluster/full chip testing with random & corner test scenarios. Through an aggregrate metrics based schedule estimate, we offer you 100% functional and code coverage (line, block & toggle coverage) for an executable verification plan.
Maximum 3 iterations for DRC/LVS clean GDSII
Based on expertise in technologies ranging from 45nm to 180nm with different processes and experience in tape-outs to foundries like TSMC, CHARTERED, UMC, TI & TOSHIBA, our engineering team is capable of handling large SoCs all the way to GDSII generation with maximum 3 iterations on DRC/LVS/ANTENNA clean-ups on industry standard sign off tools.
Benefits:
Vast domain and technical expertise combined with flexible design & verification methodology competence that ensure faster, viable, first-time-right solutions for our customers
CMMi Level 3 processes based Quality management system
Project management following our tried and tested Amplified Offshore Model that ensures a proactive and comprehensive interaction with customers providing complete visibility at each stage of the project
PMI qualified project managers
Proven track record in successfully setting up of offshore/ near-shore design centers
Confidentiality:
In all our ASIC services projects, eInfochips is committed to ensuring protection of customer's IP. This is ensured through various means - signing NDAs, isolating development teams, prohibiting discussion of the project or exchange of technical information outside the team and maintaining classified access to all project documents.
