eInfochips has developed a host of Verification IPs for standard interfaces that are integrated with OVM environment. eInfochips has built a 30-engineer OVM trained team to develop, support and integrate into designs, future OVM compliant IP initiatives.

OVM Compliant/Ready VIPs:

Being a Mentor Graphics Questa Vanguard program member, eInfochips has proven expertise on Questa verification platform which enables us to qualify VIP and provide early support on OVM. As a long-time Cadence Verification Alliance member, eInfochips has expertise in Cadence® Incisive® Plan-to-Closure Universal Reuse Methodology (URM) enabling us to provide you all encompassing support on OVM platform.

Besides, being a recognized OVM Partner, einfochips can help facilitate the development and usage of plug-and-play verification IP (VIP) written in SystemVerilog (IEEE 1800), SystemC® (IEEE 1666), and e (IEEE 1647) languages leveraging true SystemVerilog interoperability with a standard library and a proven methodology.

About OVM:
The OVM is the result of joint development between Cadence and Mentor Graphics to facilitate true SystemVerilog interoperability with a standard library and a proven methodology. It and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is based on the IEEE 1800 SystemVerilog standard and is non-vendor specific and is interoperable with multiple languages and simulators.