Image Sensor Chip

Executive Summary

Our customer is leading provider of image sensor chips.

The image sensor chip has 96 timer module instances and 14 output clocks. The digital block also latches the incoming pixel data and formats it. The chip contains both digital and analog portion. The chip is working on 300 MHz, mapped with 180nm technology and contains four metal layers. It had 165K instance, two macros, two main clock domains, and 14 generated clocks.

The customer had an in-house expertise for analog and mixed signal design while looking for solution provider for physical design of digital block of the chip.

The customer selected eInfochips based on proven track record of successfully managing complex physical design projects involving advanced process technology nodes and low power design techniques.

eInfochips delivered complete physical design solution for the digital block including synthesis, P&R, physical verification and sign-off. eInfochips developed complete flow for RTL-to-GDSII, performed all sign-off services - timing, power, DRC/LVS/ANTENNA, and delivered final GDSII to tap-out the chip on time.

The Customer

Our customer designs, develops, and manufactures leading edge Image Sensors serving the Consumer, Industrial, Scientific, and Automotive markets. Image Sensors are developed using the leading edge technologies that enable sensors with the performance of a CCD and have the benefits of CMOS.

The Challenge

  • To achieve timing requirements on DDR interface
  • To resolve congestion because of availability of only four metal layers
  • To achieve slew requirement using manual routing as tool was routing long wire as floorplan was rectangle

The Solution

eInfochips team worked on the following aspects as part of the physical design effort:

  • Development of timing constraints for the RTL and standard cell library provided by client
  • RTL synthesis and P&R is done using Magma tool chain
  • Scripts and directory structure are prepared as per eInfochips flow setup guidelines
  • Physical design includes synthesis, floorplaining, powerplanning, placement, CTS and final routing
  • Sign-off flow comprised of:
    • RC extraction
    • Final timing reports
    • Area reports
    • Power reports
    • DRC/LVS/ANT reports
  • Delivered final GDSII file, timing, area, power reports to the client

Technology

  • Industry: Video
  • Technology: 180nm Tower (4 Metal layers)
  • Design Complexity: 165K Instances, 2 Macros
  • Frequency: 300 MHz (Max.)
  • Tools: Magma tool chain

The Benefit

  • Delivered complete physical design solution enabling customer to successfully tap-out the chip on time
  • Developed the constraints and necessary timing feedback about RTL to designer for resolving RTL/architecture issues