Full chip verification of ARM based 2G/3G chip

Executive Summary

Our customer is a leading wireless technologies solutions company.

The chip has one main ARM processor that resides in Layer 2/3 to communicate with each and every sub-system, components and peripherals in the chip. There are also other major sub-systems like 2G, 3G to support various multiplexing technology. The chip supports USB interface, three independent JTAG interfaces, two I2S interface & four USIF interfaces. This chip is targeted at mobile phones and data cards for internet connectivity.

The customer was looking to outsource full-chip verification to a company that has had a history of verification success and a skilled team conversant with the latest verification technologies and methodologies.

Based on this criteria, the customer engaged eInfochips, for development and debugging of system level test cases, to verify chip functionality and generate coverage reports. eInfochips team performed thorough verification in the scheduled time period despite dealing with complex mixed language based verification environments and continuous changes in the chip architecture.

The Customer

Our customer has been a pioneer in the development of Media Independent Handover (MIH) and helped define the IEEE 802.21 standard for seamlessly connecting GSM, WCDMA, WiMAX, Wi-Fi, CDMA2000, and virtually any other radio access technology. The customer licenses advanced enabling solutions to semiconductor companies and wireless device manufacturers, including middleware for seamless connectivity across any air interface technology.

The Challenge

  • The biggest challenge was multiple verification languages (VHDL, SystemVerilog, DSP Assembly, ARM Assembly, and C++) along with complex verification environment that requires excellent debug skills as well as system level understanding to identify the issues.
  • Continuous changes in the architecture of the chip led to prolonged and inefficient RTL debugging.

The Solution

We offered the following ASIC Verification services:

  • Prepared verification test plan and test cases for component level and sub-system level verification
  • Traced and debugged RTL to unearth exact cause of RTL bugs
  • Implemented scripts for fast and secure verification
  • Followed processes to update and review the test plan and coverage plan
  • Generated coverage reports, provided coverage analysis to designer for code coverage holes and implemented new tests to achieve 100% code coverage

Technology

  • Industry: Networking
  • Technology: 2G, 3G, HSDPA, GSM, CDMA
  • Gate Count: 18 Million
  • Methodology: Mixed Language
  • Languages: VHDL, SystemVerilog, C++, DSP Assembly, ARM Assembly
  • Tools: Questa, ModelSim

The Benefit

  • Multi-tasking approach ensured project was executed in the defined timelines
  • Value added contributions in complex System Level Verification by closely working with Designers and onsite Verification Engineers
  • Innovation in methodologies for performing thorough RTL analysis