FPGA Design of an IP based Audio Video Distribution System

Executive Summary

Our customer is the undisputed world leader in digital entertainment networks based on Internet protocol (IP) technology.

The FPGA based Audio Video Distribution System is designed to distribute an uncompressed A/V stream through a standard gigabit TCP / IP network. It supports s–video, composite video, component video (up to 1080i resolution) and VGA video streams as well as analog and S/PDIF audio streams. Apart from A/V encoding and decoding, it also implements UART, IR and digital IO interface to provide user flexibility and ease of use.

Our customer planned to develop a complex video / audio distribution system that would operate at high frequencies. Based on a meticulous past record of FPGA design, verification and system level testing, eInfochips was signed on to perform FPGA design and functional and gate level verification of the IP based video audio distribution system. By the end of the engagement, our team successfully delivered a complex video/audio distribution system operating at high frequencies and multiple clock domains.

The Customer

Our customer provides IP-Based & IP-controlled systems, designed for residential and commercial use, that can handle any number of digital or analog sources and deliver uncompressed content, including high definition audio and video, to an unlimited number of zones. By combining content and control signals in one data stream, the systems offer new levels of affordability, simplicity, reliability, and expandability, benefiting both installers and end-users with lower costs for installation, set-up, and support.

The Challenge

  • Constantly changing interface specs called for a number of dynamic changes in the design and verification environment
  • Synchronizing data and controls in a multi-clock domain (ranging from 1 MHz to 200 MHz)

The solution

eInfochips' team offered the following RTL design & verification services

  • Defined functional specifications, core architecture
  • RTL design, implementation and integration in Xilinx Spartan 3E (XC3S500E) device
  • Developed the following features for the synthesizable RTL core:
    • Serves as a bridge between TI's DM642 Digital Signal Processor through External Memory Interface (EMIF) and various on-board Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC)
    • Interfaces DM642 Video Ports with the on-board Video Decoder and Encoder ICs
    • Implements PCM and Bi-phase S/PDIF audio encoder and decoder
    • Serial interfaces controller such as UART and IR transmitter and receiver
    • General Purpose Input Output (GPIO), PWM generator and Programmable Timer
  • Designed and developed a verification environment to check the FPGA core at functional level as well as gate level, offered 99% functional coverage
  • Performed synthesis, PAR and Timing analysis using Xilinx ISE

Technology

  • Industry: Video
  • Technology: PCM Audio (44.1 Kbps), SPDIF Audio (32 to 192 Kbps), YUV to RGB Color Space Conversion, UART Transceiver, IR Encoder and Decoder
  • Device: Xilinx Spartan 3E 500 (85% Usage)
  • Frequency: 200 MHz
  • Languages: Verilog
  • Tools: VerilogXL, NCVerilog, XILINX ISE

The Benefit

  • Developed a cost–effective and highly efficient audio video distribution system on Xilinx Spartan 3E FPGA (XC3S500E)
  • 100% timing enclosure & 99% functional coverage
  • eInfochips’ coding style ensured every element on the FPGA is utilized most effectively