FPGA Design for Telecom Switch Platform

Executive Summary

Our customer is a telecom network equipment supplier.

telecom-switch-fpga.jpg

The Network Processing Card (NPC) has two FPGAs. The main function of this card is the take the Ethernet data from 10G MAC / XAUI interface, add some header information and pass it to the other card in the system. Some processing and decision making regarding bandwidth utilization is also done in this NPC card. The system is suitable for Metropolitan Area Network (MAN) deployments, particularly where the intention to converge many service types into one network.

The customer has been developing telecom switch platform based on patented technology that alters the cost equations of operating networks by simultaneously simplifying network architecture and operations while bringing dramatic improvements in performance. The customer was looking for strategic outsourcing partner in development of FPGA based solution for telecom switch platform with an ability to provide comprehensive services - RTL Design, FPGA Implementation, Timing Analysis, Board bring-up and Debugging within aggressive timeline and significant cost benefits.

eInfochips served the objective of customer by means of FPGA design for telecom switch platform with complexity of 100K gates. With the expertise that eInfochips team had in the design of high end systems targeted in FPGA, the RTL design, Synthesis, FPGA implementation was performed successfully.

The Customer

Our customer’s vision is to provide a programming interface into the very heart of the network in order to solve the problems of quality of experience for network users. Based on a technology breakthrough, the customer has designed a set of network equipment products that will make the network tunable for any service, anytime, anywhere. The customer has shipped many products worldwide to major technology companies including tunable laser manufacturing software, transponders and subsystems and optical sensing products.

The Challenge

  • To deal with frequently changing requirements as sub-block level architecture was unstable
  • To extract and understand the functionality of each block using diagrams only
  • To redevelop RTL code as per latest coding guidelines for already delivered blocks
  • To deal with many problems in board level validation because gate level simulation was not performed as per customer’s instruction

The Solution

eInfochips team worked on the following aspects as part of the FPGA design effort:

  • Development of RTL code using VHDL for LPID, WRED, OWDi and OWDe blocks
  • Development of RTL code using VHDL for two FPGA systems of NPC
  • Implementation of XILINX XAUI / 10G Ethernet MAC core in the design
  • Implementation of DDR interface working at internal frequency of 500 MHz
  • Performed synthesis using Xilinx ISE 11.3 tool, timing analysis and chip level integration
  • Implementation on XILINX Virtex-5 FPGA and board level validation

Technology

  • Industry: Communication & Networking
  • Technology: XAUI / 10G Ethernet MAC, DDR
  • Device: Xilinx Virtex 5
  • Gate Count: 100K
  • Frequency: 500 MHz
  • Languages: VHDL
  • Tools: XILINX ISE 11.3

The Benefit

  • Complete ownership from design to board bring-up
  • The FPGA was successfully demonstrated to work at full speeds and fully complied with the performance requirements stated by the customer
  • Technical expertise displayed by the eInfochips team in the on-schedule and on-budget design of a 100K gate count FPGA