FPGA Design for 10G Ethernet Test Pattern Generator

Executive Summary

Our customer is a worldwide leader in Networking.

The FPGA consists of multiple 1G and 10G Ethernet ports connected to Ethernet switch via XAUI and High speed MGT. Other blocks include PowerPC core, Memory controller and primary to secondary FPGA interface and custom logic for synchronization. The main application of this FPGA based design is to provide an interface to multiple DSPs for uncompressed video-audio transfer via secondary FPGA and to multiple boards via 1G and 10G Ethernet Ports.

Our customer initiated development of a new generation 10G Ethernet based solution with a vision to retain its supremacy in the networking industry. The product development team grew more than expected and timelines began to shrink. The only solution was to associate with a reputed ASIC services company that could serve as an extended arm of their R&D team.

eInfochips was chosen for the development of an FPGA based design, verification and board level validation of 10G Ethernet Test Pattern Generator. Our team ensured that the RTL design, implementation and testing was completed on time, meeting area and timing constraints along with synchronization in a multi-clock design.

The Customer

Our customer offers best in class products and services in Network Systems, Voice and Video Communication, Network Security, Wireless / Mobility, and Data Center. The company serves Consumer, Commercial, Public Sector, Enterprise, and Service Providers networking solutions in Data, Voice, Video and Mobility.

The Challenge

  • To achieve synchronization in a Multi-clock design
  • To meet area and timing requirements of a complex design

The Solution

eInfochips offered the following RTL design, verification, and validation services:

  • Developed Functional / Design specs of 10G Pattern Generator and synchronization modules
  • Developed RTL , module level verification environment and test cases for all the above modules
  • Integrated the design in EDK environment, performed FPGA synthesis, Place & Route, Timing Analysis, Board level testing and Validation

Technology

  • Industry: Networking
  • Technology: 10GMAC, XAUI Interface
  • Device: XILINX Virtex-5 FXT(60% Usage)
  • Frequency: 156 MHz
  • Languages: Verilog
  • Tools: ModelSim, XILINX ISE 10.1i, and EDK 10.1i

The Benefit

  • Turnkey FPGA design solution
  • eInfochips' team successfully implemented and synchronized the design on a multi-clock domain with main core frequency of 125MHz and maximum operating frequency of 156 MHz