Development of Synthesizable AHB Verification IP

Executive Summary

Our customer is a world leader in electronic design automation (EDA).

The synthesizable AMBA AHB 2.0 VIP provides a quick and efficient way to verify AMBA SoC designs by implementing advanced techniques for more productive verification. The VIP includes the following components: AHB Master BFM, AHB Slave BFM, AHB BUS Arbiter, AHB BUS Decoder, Message Decoder, Message Encoder, Clock Control, Coverage Monitor, Error Monitor, Hardware Abstraction Layer (HAL) Ports.

The customer was looking for a complete solution partner to design as well as verify synthesizable AHB Verification IP. eInfochips' team developed VMM based verification component with Standard Co-Emulation Modeling Interface (SCEMI 2.0) connecting transaction-level models with CHIPit automated rapid prototyping platform to achieve efficient and faster simulation.

The Customer

Our customer supplies the global electronics market with the software, IP and services used in semiconductor design and manufacturing. Customer's comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give its customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk.

The Challenge

  • To implement Clock control mechanism for CHIPit platform as it is using SCEMI 2.0
  • To synthesize RTL and run it on CHIPit prototyping board
  • To resolve reset mechanism on CHIPit platform
  • To achieve simulation speed and debug any issue on CHIPit platform

The Solution

eInfochips’ team worked on the following aspects as part of the verification IP development:

  • Implementation of full AHB features compliant to AMBA AHB 2.0
  • Development of synthesizable AHB master & slave VIP components with verification environment & H/W integration
  • Synthesizable AHB Master & Slave Transactors
  • AHB master & slave SystemVerilog components with SCEMI2.0 interface
  • Development of verification environment and test cases for different scenarios supported by protocol as per functional specification
  • Working demo with AHB Sub System using ChipIT Board
  • Documentation: Functional Spec, Implementation details, User Guide etc.

Technology

  • Industry: Semiconductor – EDA
  • Technologies: AMBA AHB 2.0
  • Languages: SystemVerilog
  • Methodologies: VMM, SCEMI 2.0
  • Tools: VCS, CHIPit Prototyping Platform

The Benefit

  • Achieved reduction in simulation time by designing BFM with internal CRC to check the data integrality
  • Hardware BFM is capable to generate 65356 AHB transaction automatically by designing constraint solver inside the hardware
  • Achieved 100x Performance Gain (with CHIPit board) over simulation
  • Delivered composite solution for higher coverage achievement with less number of test-cases