Our client is a leading developer of DDR DRAM memories, memory controllers and interface IP. We have successfully developed a behavioral model for our client's DDR IO Cell.

Introduction

The DDR IO Cell is a high-performance, low latency controller interface to DDR-based DRAM memory system. The general-purpose cell is independent of logical memory controller design, enabling support for a wide variety of memory applications that need high bandwidth and low latency. The DDR IO performs data serialization and de-serialization functions associated with write and read operations. A 2-to-1-serialization ratio is supported. The DDR IO cell comprises of one 12-bit request bus block, one control block, and a variable number of data blocks. The control block performs register access, initialization, maintenance and testability functions.

Block Diagram

eInfochips Role

eInfochips role was to develop a Verilog behavioral model for DDR IO Cell.

This included -

• Defining DDR IO cell model micro-architecture
• Developing a fully functional Verilog DDR IO cell model
• Supporting integrations with client's environment
• Documentation, user guide for DDR IO cell behavioral model
  

How this was achieved

• DDR IO cell functionality understanding
• Internal architecture development by sub module partitioning
• Internal architecture review
• DDR IO cell behavioral model integration with verification environment