Beamformer Chip Verification

Executive Summary:

Our customer delivers semiconductor and systems solutions with high content derived from the company's intellectual property.
Beamformer Chip Verification
The next generation receive beamformer ASIC is targeted for 2D ultrasound machine supporting color Doppler. The highly integrated ASIC leverages all the benefits of customer's award-winning technology in offering the industry's lowest power consumption and highest performance compared to current FPGA-based implementations. The highly configurable ASIC provides the flexibility for ultrasound OEMs to simplifying software and system design thus speeding time to market for a wide range of machines from ultra-low power handhelds, through mid-range and high-end carts.
The customer engaged eInfochips on the basis of sound expertise in ASIC verification including chip level verification, test bench design using latest verification methodologies, code coverage & functional coverage. eInfochips team developed an UVM based verification environment using SystemVerilog and register model to execute complete ASIC verification successfully.

The Customer:

Our customer is a technology company focused on delivering innovative semiconductors, modules, and subsystem solutions to the ultrasound industry. The customer also provides IP, to other medical imaging industries including CT, as well as to the wireless infrastructure and high-performance computing industries.

The Challenge:

  • To integrate customers' available software flow with verification environment using flexible DPI(s) so as to re-use software flow for system programming and writing tests
  • To integrate customer's C model (algorithmic model) with new verification approach so as to re-use C Model for pattern generation and matching

The Solution:

eInfochips team worked on the following aspects as part of the verification effort:
  • Complete verification of ASIC
  • Chip Level Verification
  • Test Bench Design using Most latest Verification Technology - UVM
  • Use of Register Model
  • Re-use C Model available for Beam algorithm in System Verilog Environment
  • Key deliverables:
    • Coverage Plan, Coverage Module,
    • Test Plan
    • Verification Environment Code
  • Achieved 100% Functional Coverage and Code Coverage
  • Use Doxygen for documentation by writing comments within the source code

The Technology:

  • Industry: Medical
  • Technology: Medical scan processing devices (MRI, Ultrasound, Echo)
  • Languages: SystemVerilog
  • Methodologies: Universal Verification Methodology (UVM)
  • Tools: Questa 10.0b

The Benefit:

  • eInfochips enabled customer to develop ASIC addressing a critical gap of cost, performance, & large size offered by the current FPGA implementation of these devices.
  • Developed flexible and re-usable Verification Environment using UVM & SystemVerilog which can support customer's next generation chip too.
  • Delivered verification solution allowing customer to re-use their software flow to achieve co-verification
  • Complete verification of receiver chip using latest verification approach in short time span with higher coverage
  • Identified bug in early stages and provided exhaustive verification plan and executed with accuracy