ASIC Physical design of PCI Express Switch

Executive Summary

Our customer is the global leading supplier of PCI Express switch and bridge products.

The PCI express switch contains 24 ports and 96 lanes. Each port had 96 lanes, making a total of 24x96 lanes. The flip-chip included blocks like Processor, six Stations, and nine SerDes & DDR3 Memory Controllers. There are mainly six blocks that are instantiated many times in the chip. Each block has more than 3M gates and more than 5K I/O interfaces.

The customer had an ambitious plan to be pioneers in delivering PCI Express Gen 3 switch samples using 90nm and 40nm process technology. In order to achieve this objective, the customer was looking for an established ASIC services outsourcing company with physical design expertise for complex PCI Express chips.

eInfochips was their unanimous choice based on our track record in this domain. We delivered Netlist to GDSII services for the 25 million gate multi-clock domain PCI Express switch flip chip on 90nm and 40nm technologies. eInfochips' team successfully performed place and route of the PCI Express flip chip using proven physical design flow. Congestion issues were resolved by creating blockages to guide P & R and developing scripts for timing and area optimization.

The Customer

Our customer has been developing I/O interconnect devices since 1994 and is a public company. Originally focused on PCI-based products, it was a natural progression to develop products based on PCI Express (PCIe) while offering the broadest range of devices and fullest feature-set in the market. The customer has shipped over three million PCIe devices.

The Challenge

  • Congestion due to rectilinear block shapes and reduced die size of the chip
  • Implementation of low power design techniques – Power Gating , Voltage Scaling on 40nm process technology
  • Achieving timing and slew targets, custom routing and placing of over 31 macros in one of the blocks

The Solution

eInfochips' team (Team size of 8 Engineers) worked on the following aspects as part of the physical design engagement:

  • Netlist to GDSII implementation for 6 blocks
  • Block-level synthesis
  • RTL synthesis and DFT using DC (Design Compiler)
  • Constraints adjustment for the I/O - we automated the flow and created I/O constrains for all the blocks
  • Floor-planning, power-planning, timing closure, CTS and detail routing, crosstalk noise analysis, crosstalk delay analysis, EM/IR drop analysis, power analysis, DRC/LVS clean layout
  • Physical layout of 15 million gates multi-clock domain IP

Technology

  • Industry: Networking & Communication
  • Technology: 40nm, 90nm - TSMC
  • Design Complexity: 25 Million Gates
  • Frequency: 250 MHz
  • Tools: Magma (Talus Design, Talus Vortex), Synopsys (PrimeTime, Hercules, Star RCXT, Formality)

The Benefit

  • Physical Design, Sign off STA & Physical Verification of a multi-million gate PCIe switch was delivered on time
  • eInfochips took the complete ownership of delivering GDSII to foundry allowing customer to focus on core competencies like designing features/functionality and customer enabling
  • Managed and supported the customer’s tape-out successfully