Our customer is a major supplier of computing and communications products such as chips, boards, systems and software building blocks The project involved physical layout of a 3 million gate multi-clock domain IP. Multiple IP cores like PCI, SPI, DMA, VGA, USB available in OSI-System on Chip were integrated using a common bus interface called WISHBONE.

Block Diagram

eInfochips’ Role

• Physical synthesis of RTL
• Generating scripts for constraints, I/O and macro placement
• Static timing analysis of the netlist
• Design Partitioning · Floorplanning
• Core ring, block ring, power stripes generation
• Placement and clock-tree synthesis
• Signal integrity
• Analyzing timing report and solving timing violations
• DRC/LVS cleaning of the design
• Design analysis of Power, IR-drop and EM
• ECO updates and parasitic extraction

Tools Used

• Cadence PKS for physical synthesis
• Cadence SOC-Encounter for netlist to GDSII
• NanoRoute for detail routing
• Voltage storm for power analysis
• Celtic for SI analysis

How this was achieved
The project was a successful onsite engagement with a team of 4 layout engineers and 1 project leader for duration of 4.2 months.

Technical highlights of the project
The design had 4-clock domain, 3 Million gates, 78 memory blocks and works at the maximum frequency of 278 MHz. eInfochips used the following techniques to meet the challenges of the design.

• Design partitioning for suitable size block
• IO and macro placement done manually using fly-line analysis
• Boundary registers placed near IO
• Cluster based placement and clock tree synthesis
• IR-drop analysis done after trial routing
• Extra power stripes provided at center of core
• Effective use of the scripting done
• STA to accommodate the delay due to voltage