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Verification of OC-192 line card framer chip

Our customer is a US based company, an established world leader in design and manufacturing of communication infrastructure. This product is used for broadband services to fine-tune the bandwidth allocation to customers without service outage resulting in lower costs.

eInfochips’ Role:

  • Understanding of system and study of functional specification of blocks
  • Creating comprehensive Test Plans for the individual blocks
  • Architecting verification environment (VE)
  • Coding and integrating the VE using existing 'e' Verification Components (eVCs) like SONET and UPI.
  • Verification at block level and mini chip level
  • Analyzing functional and code coverage

How was this achieved?

eInfochips achieved this task with a team of five ASIC Verification engineers for duration of 6 months. The total effort was 28 man-months.

  • SONET/SDH/OTN framer/mapper chip with virtual to contiguous concatenation conversion and reverse support
  • Development of Verification environment for functional verification at the block level as well as mini chip level
  • Use of SONET, UPI and Scoreboard eVCs in the Verification enviornment
  • Tools: Specman, Modelsim
  • Platform: Windows XP, Solaris, Linux

Conclusion:

  • Reusable eVCs can help in expediting the verification process
  • It is possible to develop reusable test cases that can be used at all levels of functional verification

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