Design IP can be used to overcome the productivity gap and time-to-market pressure in SoC design cycle. Over the years, eInfochips has built a high level of expertise in Digital ASIC Intellectual Property development. eInfochips has comprehensive experience in all aspects of SIP development including definition, architecture design, algorithm development, RTL coding, verification, synthesis, FPGA implementation and testing. eInfochips offers different products and turnkey solutions in the Digital Design IP Core domain such as video processing IPs, peripheral IPs, memory interface IPs, and bus protocol IPs, which can be easily integrated with any third party IP and SOC platform to reduce the development time. The design entry of these Semiconductor IP cores is done in Verilog HDL. These are fully synthesized IP cores, designed to be optimal in terms of power, speed and area and are tested on Xilinx / Altera FPGAs. eInfochips also offers Silicon IP Development which can be targeted as ASIC Design IP or FPGA Design IP as per customer's requirement. We develop ASIC IP Core and FPGA IP Core as per industry standards that can be easily reusable, customizable, and interoperable. Also we provide ASIC IP Evaluation, Design IP Selection, Design IP Verification, Design IP Enhancement and Maintenance Services as a part of Design IP core development.
| Design IPs | |
|---|---|
| Bus Protocol |
AHB to APB Bridge, SPI4.2 , APB to slave interface, AXI Slave, DDR, NAND Flash Controller , PCI master & target(FPGA tested) |
| Video Processor Core |
CCIR656, GCR, AES, IMR, IDCT, DCT, LUT FIR, DPRAM FIR, Reed Solomon Encoder |
| Serial Protocol |
SPI 3, SPI 5.0, UART |
| Embedded Processor |
e80186 |
eInfochips provides reusable design intellectual property core development and associated maintenance and sustenance services.