20090630-VMM-EnabledMIPI®CSI-2-DSI-HSI-SDIO

eInfochips Announces VMM-Enabled MIPI® CSI-2, DSI & HSI and SDIO Verification IP for the Synopsys® DesignWare® Verification IP Alliance Program

Sunnyvale, CA and Ahmedabad, India, June 30, 2009: eInfochips Ltd., a leading design services company today announced the availability of Verification Methodology Manual (VMM)-enabled MIPI® CSI-2 (Camera Serial Interface), DSI (Display Serial Interface), HSI (High Speed Synchronous Interface) & SDIO Verification IP (VIP). The eInfochips VIP has also been added to the Synopsys DesignWare® Verification IP Alliance Program. The Alliance program gives designers access to a broader range of VMM-enabled verification IP, which complements DesignWare Verification IP portfolio. Synopsys selected and qualified eInfochips for the Alliance program because of its extensive experience in verification, VMM methodology and verification IP development.

“The addition of eInfoChips’ MIPI and SDIO VIP to the DesignWare VIP Alliance Program further expands the broad range of VMM-enabled verification IP that is complementary to the DesignWare portfolio” said John Koeter, vice president of marketing for the Solutions Group at Synopsys. “With eInfochip’s extensive experience in VMM-enabled verification IP, designers can have confidence that the verification IP can be easily integrated into System-Verilog verification environments, helping to speed testbench development efforts.”

eInfochips' VMM-enabled MIPI CSI-2, DSI & HSI, and SDIO VIP products are based on the layered architecture of object oriented programming that allows coverage-driven verification suitable for verifying transmitter and receiver with either of them as the design-under-test (DUT). ”

MIPI CSI-2 VMM-Enabled Verification IP More information available at http://www.einfochips.com/asic-fpga-ips/mipi-csi-2.php
MIPI HSI VMM-Enabled Verification IP More information available at http://www.einfochips.com/asic-fpga-ips/asic-fpga-ips/mipi-hsi.php
SDIO VMM-Enabled Verification IP More information available at http://www.einfochips.com/asic-fpga-ips/sdio.php

Deliverables

Deliverables include verification IP encrypted code, sample test bench and test cases, user guide and release notes.
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