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1. Design
complexity requires system-level design
The ambiguity of product specifications written in a natural
language often introduces design flaws that go undetected until
later, making the solution more expensive. The focus on system-level
design has become greater as design complexity has increased. More...
- By Gabe Moretti, Technical Editor
2. Plug and Play Design Methodologies for FPGA-based Signal
Processing
FPGAs are a good fit for applications that demand higher
performance than what DSP processors can offer, yet do not meet
the criteria to justify ASIC economics. More...
-By Narinder Lall, Xilinx, Inc and Eric Cigan -, AccelChip, Inc.
3. A Methodology for DSP-Based
FPGA Design
Overall, DSP is becoming a highly ubiquitous technology,
seeing its application not only in a myriad of consumer, automotive
and telephony products, but also in an increasingly advanced class
of devices. More...
-ByAndrew Dauman and Dirk Seynhaeve Synplicity, Inc.
4. Co verification
Methodology for Platform FPGAs
To ensure a fast and efficient implementation of advanced,
feature rich FPGAs, designers need access to the latest in productivity
enhancing EDA tools and methodologies. For years, hardware/software
(HW/SW) coverification has been commonly used to debug ASIC SoC
designs. More...
-By Milan Saini and Ross Nelson, Xilinx, Inc.
5. On-Chip
Power Integrity, Including Package Effects
On-chip power integrity effects and their influence on the entire
power delivery system have become a major concern in the design
of large and complex high-speed SoC designs. Today's extreme design
challenges require a complete power-aware solution that encompasses
the global effects of the entire power delivery system, including
the realistic effects of the package and the PC board on the functional
operation of the IC. More...
- By John Kane and Jiayuan Fang, Sigrity, Inc..
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Technology Showcase
Unlike the 10 Gbps FC standard that
is not backward compatible, 4 Gbps products can work with
2 Gbps and 1 Gbps product. The transition from 1 to 2 Gbps
FC is almost complete. 4 Gbps products will gain traction
now.
Read More..
-By Venkatesh Ganesh
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eInfochips
Partner Showcase
The white paper explains the major
decisions in architecting an SOC and guides the designer to
a systematic approach to design structure using processors
as the fundamental building blocks of the SOC.
Read More..
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eInfochips Corner
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Featured
Product
DDR Design IP core
Depending on the application, DDR
custom interface can be used as a SDR or DDR SDRAM controller.
DDR is used to interface any industry standard (SDR or DDR)
memory device to a host model (an embedded processor or a
system), which drives the core to access SDRAM.. More...
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Client Success
Story
Verification of Personal Video Recorder on a chip
The video-processing chip delivers
higher quality and low cost PC video solutions. The technical
highlights were development of a single low-power, low-cost
chip implementation for desktop and notebook PCs. Having worldwide
multi-standard Audio decorder with DVD quality MPEG-2 Encoder.
More...
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News
The emergence of electronic products
indigenously designed specifically for the Indian and regional
markets. This will spur the development of product definition
and architecture skills necessary for any product design activity.
.
Read
More..
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