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Monthly Newsletter March 2010,Vol VII Issue II

eInfochips' Corner

Featured Success Story

Video Application Framework more...

Technology Showcase

Semaphore: A Crucial Entity in verification more...
Designer's Corner

Almost 60-70% of time in the ASIC cycle is occupied by Functional Verification and so, the main aim of this paper is to provide overall guidelines in verification.more...

Partner Showcase

Texas Instruments' OMAP™ 4 platform debuts, revolutionizing the Mobile Internet experience more...

Event

Visit eInfochips at CDNLive! EMEA 2010 is the fifth annual Cadence® EMEA user conference - Munich, Germany (4th-6th May, 2010) more...

Featured Success Story

Video Application Framework
eInfochips' Video Application Framework (VAF) provides a proven modular framework to accelerate time to market for developing video infrastructure products. VAF combines video capture, encoding, packetization and streaming modules for TI DaVinci platform based development. The VAF can be easily ported to other embedded platforms, and is available for the Linux OS. Read more...


Technology Showcase

Semaphore: A Crucial Entity in verification
Semaphore is a crucial entity which serves towards creating effective testbench to generate heavy traffic on chip interfaces.
Read more...

-By Milan Pujara – eInfochips

Partner Showcase

Texas Instruments' OMAP™ 4 platform debuts, revolutionizing the Mobile Internet experience
Forging new pathways to the mobile future, Texas Instruments Incorporated (TI) has highlighted how its OMAP™ 4 platform spurs some of the industry's most sophisticated user experiences … Read more...

partner showcase

1. Using FPGAs to build battery-free RAID cache memory systems
Increasing performance demands from applications in enterprise finance and Web 2.0 are causing data center designers to look for more cost-effective, alternative approaches to today's battery-backed data recovery systems.Read more...

- By David McIntyre.

2. FPGA synthesis can be a leverage point in your design flow
Large, complex FPGA devices pose significant challenges to an FPGA project team. Only by following sound design flow practices can FPGA designers manage their projects effectively. Read more...
- By Sanjay Thatte

3. Improving Software Development and Verification Productivity Using IP Based System Prototyping
This paper will review different use models driving requirements for intellectual property (IP) models in different project stages. Introduces System Prototyping as a solution, which combines the advantages of virtual prototypes with rapid prototypes. Read more...
- By Frank Schirrmeister

4. A Recipe for Verification IP - The Role of Methodology
This paper will emphasize how a recipe that combines methodologies provides a superior VIP, one that reduces effort and debugging time, while avoiding reference to specific EDA tools when possible. Read more...
- By Amit Tanwar

5. Partitioning an ASIC design into multiple FPGAs
Today's FPGAs are large enough to contain a complex system-level design. It's practical, however, for these designs to be partitioned among several FPGAs for various reasons.Read more...
- By Juergen Jaeger


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eInfochips is a technology design services & solutions company having own IPs & offering services in ASIC/FPGA, Embedded Systems and Software products and applications since 1995. Our customers
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Tip of the Month

Guidelines for complex SOC verification

--By Jignesh Oza
(Published in embedded.com & techonlineindia.com)

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