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eInfochips' Corner
| Technology Showcase
Grounding in Mixed Signal PCB
Depending upon your application, there can be signals on your printed circuit board from both analog and digital worlds. The crosstalk and the switching noise from the digital signals can alter the shape and hence, meaning of analog signals. This makes it necessary to shield and isolate sensitive analog signals from noisy digital signals on the PCB. Read more...
- By Bhavishya Goel, eInfochips
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Partner Showcase
Embedded video development is speeded by DSP system level abstraction
APIs provided by TI's new DSP architecture enable developers to focus on applications without having to spend much time with video implementation issues and without having to program a DSP. Read more...
- By J.B. Fowler, Texas Instruments
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Featured
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Verification of Networking SoC
We served High Sigma (Zero Defect) quality SoC verification services for a chip-set, multi-million gate VLSI devices targeted for storage area networking (SAN) needs. With multiple Giga-bits/second throughput, the SoC delivers scalability, portability and comprehensive solutions as per the need. Read more... |
1. Automated Formal Verification of OCP based IPs using Cadence's OCP VIP library
The automation of Formal Verification (FV) is one possible solution to address the above problems. Complementary to well-established pseudo-random verification techniques, FV enables the verification engineer (or the designer) to exhaustively prove specific parts of a circuit. This paper discusses the automation of FV for bus protocols like OCP. Read
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- By
Jeroen Vliegen
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USB Host IP-Core Hardware and Software Concurrent Development
This paper presents a based on behavioral synthesis design flow that allows high-quality hardware and software design of IP-Cores. The main flow's advantage is that it allows hardware and software to be developed concurrently, reducing design time.
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- By
Adelmario Douglas, Renata Bezerra, Diogo Maciel, Antonyus Pyetro, Edna Barros
3. A Chip IP Integrator for System Level Design
This paper describes a new approach for chip design and system-level integration. A hierarchical RTL context-preserving insertion and connectivity methodology has been further implemented in EDA tool – chip IP integrator. Read
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- By
Mikhail Baklashov
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Achieving Yield in the Nanometer Age
In the nanometer era, yield success is much harder to achieve, because of the increased number and complexity of variables affecting manufacturability. The designer's strategy must shift from simple design rule compliance to the definition and design of the optimal layout for the highest yield. Read
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- By Anthony Nicoli
5. Automated Test-Bench for Mobile Applications
This paper describes the design and implementation of an Automated Test-Bench Application for Mobile phones that can advance the complete development cycle of application development and validate the robustness of the solution. Read
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- By Ashwin Kumar
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