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eInfochips' Corner
| Technology Showcase
Migrating from SPI 4.2 to SPI 5 IP Core - Architectural Changes and Re-usability
High bandwidth data transfers have led to migration from existing packet interface standards to advanced ones. SPI (System Packet Interface) v4.2 has, for many years, remained an industry standard for packet based transfers from link layer to PHY layer
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-By Kaushal D. Buch, eInfochips ltd.
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Partner Showcase
NXP Unveils World’s First Integrated Dimmable Mains LED Driver IC
SSL2101 enable LEDs to operate and dim with existing infrastructure to further improve energy efficiency
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Featured
Success Story | |
| In-Vehicle Infotainment Dashboard
eInfochips has developed infotainment dashboard to provide simple solution to support multiple devices with latest media oriented protocols.
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1. PCI Express Gen 3 Simplified
A preview of what embedded developers can expect to see in the newest generation of the PCI Express interconnect protocol, doubling bandwidth and increasing end-system performance.
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- By Akber Kazmi
2.FPGAs Move To 40 nm
New FPGAs hits 40 nm and continue to push the performance envelope.
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- By William Wong
3. Tip: Implementing VoIP with software voice engines
Today's embedded processors are powerful enough to support a complete VoIP telephony subsystem without adding complex and expensive external DSP chipsets.
By Jonathan Cline
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4.FPGA outsourcing: Ten questions you should ask
FPGAs are an ideal solution for many applications. They offer an appealing mix of high performance, low cost, and low power. On the other hand, many companies find it hard to do FPGA design.
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- By Mark D. Wecht
5. How High-Level Synthesis Can Raise the Efficiency of Design Reuse
Design reuse and IP-based design are established design practices enabling fast integration of large-scale, high-complexity systems. But while silicon potential keeps improving through node shrinks, designs meant for reuse cannot leverage these technological advances due to their rigidly defined micro-architecture.Read
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- By Thomas Bollaert
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