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December 2005, Vol II Issue XII
 

 
Welcome to eInfochips' monthly newsletter - Dashboard, your source for industry news in the ASIC & Embedded world.

Top Stories of the month
1. Design hub challenges before India
2. More and Moore
3. Timing Analysis Rounds the Corner to Statistics
4. SoC value linked to software
5. Chip industry wastes energy, money, says ISMI


eInfochips Corner

Technology Showcase India: An emerging powerhouse for chip design
Partner Showcase A Quick Guide to High-Speed I/O for SOC Function Blocks
Designer's Corner

Efficiently controlling the test bench flow for SOC environment More...

Event VLSI 2006

Technology Showcase

India: An emerging powerhouse for chip design
As the industry undertakes these true SOC designs, the gate counts will rapidly increase to 10M and greater. These designs will require 90/65 nanometer geometries to meet dies size and cost targets. It will also necessitate the need for more custom back-end development (physical design services) as well as mixed-signal technologies.
- By Tapan Joshi, eInfochips Read more...


Partner Showcase
A Quick Guide to High-Speed I/O for SOC Function Blocks

The two bottlenecks in high-speed SOC block design are I/O performance and computational performance. Traditionally, the main bus of a processor core represents a major I/O bottleneck. All data into and out of the processor must pass over this main bus. Read More...

 

 

eInfochips is an Integrated Design Services company with over 350 engineers. The company offers products and services in ASIC/SoC design & verification and Embedded systems development.


Designer's Corner

Tip of the Month

Efficiently controlling the test bench flow for SOC environment

- Pranav Tailor




 

1. Design hub challenges before India
One, the emergence of electronic products indigenously designed specifically for the Indian and regional markets. This will spur the development of product definition and architecture skills necessary for any product design activity. Two, electronic design services companies must move up the value chain and develop whole products in addition to the current focus on engineering services. More...
- By Pradeep Chakraborty

2. More and Moore
FPGAs tend to have at least a one-process-node advantage over many competitive architectures. That means that their inherent architectural inefficiencies (lower logic density and higher power consumption) are masked by the improved characteristics of a more advanced process. More...
- Kevin Morris, FPGA and Structured ASIC Journal

3. Timing Analysis Rounds the Corner to Statistics
In a perfect world, fabrication of silicon ICs would be a perfectly predictable process. Not only would every chip be absolutely identical, but there would be no variations from wafer to wafer, or lot to lot. More...
- By David Maliniak, Senior Editor, Electronic Design Magazine

4. SoC value linked to software
Chip designers can no longer live by silicon alone, said analysts at last week's Gartner Dataquest semiconductor industry briefing here. System-on-chip (SoC) makers must also provide embedded software, which is where the key value proposition lies, analysts said. More...
- By Richard Goering, EE Times

5. Chip industry wastes energy, money, says ISMI
The global semiconductor industry could save itself nearly $500 million per year in energy costs — or enough electricity to power a small city — and do something for the planet at the same time, according to the International Sematech Manufacturing Initiative. More... 
- By Peter Clarke, EETimes

Event


VLSI 2006
January 3-7, 2006 Hyderabad, India
19th International Conference on VLSI Design,
Visit us at Booth #41.
To schedule a meeting at VLSI 2006 Click Here

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