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eInfochips' Corner
| Technology Showcase
System Packet Interface (SPI) 4.2 IP Core
System Packet Interface-4 Phase 2 (SPI-4.2) is a protocol used for data transfer between link layer and physical layer. It is an interface for packet and cell transfer between a physical (PHY) layer device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet over SONET (POS), as well as for 10 Gb/s Ethernet applications. Read more...
-By Kaushal Buch, Tarang Popat, Rahul Jain, eInfochips Ltd.
(Paper published on www.us.design-reuse.com)
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Partner Showcase
Easy multiprocessor design with sRIO and MSGQ
When system designers must extend battery life, many believe one chip uses less power than two.
But power-saving design techniques often turn conventional wisdom on its head. Read more...
- By Todd Mullanix, Texas Instruments
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Featured
Success Story | |
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Verification of high speed router SoC
We set up a complete Specman verification environment towards developing a complete data path platform solution for OC192c/10G Ethernet. Read more...
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1. Open Verification Methodology: Why Now?
The goal of OVM is to reduce the number of methodologies available, thereby improving the productivity of SystemVerilog users, including designers, verification engineers, VIP providers, and even EDA vendors. In order to achieve this, OVM must be completely open, enable full interoperability, provide advanced functionality, and offer a long-term growth path. Read
more...
- By
Pete Johnson
2.
Verification IP Reuse For Complex Networking Asics
Maximizing verification IP reuse improves verification productivity. The International Technology Roadmasp for Semiconductors (ITRS) projects that 75 percent of design/verification productivity improvement will come from IP reuse and 25 percent from improved EDA tools, flow, or methodologies. However, because of the variety of hardware verification languages and EDA tools, and sometimes the lack of verification strategy, reuse proves a daunting task for engineers as well as managers. Read
more...
- By
Ben Chen, Srinath Atluri, Shankar Hemmady, Rebecca Lipon
3. Designing a mobile handset? I2C bus protocol offers cost savings
From the iPhone's 23 ICs to even greater numbers of ICs on mobile devices in the future, a bus protocol must interconnect complex hardware circuitry on ever-shrinking real estate. Enter I2C.
Read
more...
- By Bryan Whatley
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Serial ATA and the evolution in data storage technology
One of the more promising storage technology solutions to develop is Serial ATA, or SATA. Before we can fully appreciate the benefits behind the SATA standard, it makes sense to look back on the history of data storage. Read
more...
- By Mohamed A. Salem
5. SystemC Mixed-HDL IP Reuse Methodology
This paper proposes a methodology which addresses the clear needs of the ever-growing SystemC mixedlanguage designs by delivering critical capabilities, including advanced verification features such as; SystemVerilog Assertions (SVA), cover-groups, SystemC Verification (SCV), and more. Potential reusability issues are highlighted which require a careful mixed-language design process and planning. Read
more...
- By Rudra Mukherjee, Gaurav Kumar Verma, Arnab Saha
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