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1. DSP:
the flavor of the week?
Signal-processing tasks make heavy demands on processors,
and architectures that lack signal-processing features usually perform
those tasks poorly. More...
- By: Jeff Bier, Berkeley Design Technology
Inc.
2. Achieving Reuse with both Modifiable IP and Configurable
IP
Many ASIC designs require the differentiation that modifiable
IP provides. Other designs have market pressures and cost constraints
that make configurable IP a better choice. More...
-By: Jeff Holm , Coreware Technology Group of LSI Logic Corp.
3. No size fits all for signal
processing on FPGA
In many cases, the ability to fit the FPGA design within
the smallest possible device is a common aim, since, even in moderate
production quantities, this can result in cost savings. More...
-By: Steve Matthews, RF Engines Ltd
4. Relational
physical design: no absolutes
One of the top 10 integrated-device manufacturers recently
achieved high-level physical design reuse with a complex double-data-rate
memory controller between projects by employing a new methodology
for reuse. More...
-By: Lane Albanese , ReShape Inc.
5. Reuse
of Analog Mixed Signal IP for SoC Design: Progress Report
System-on-chip (SoC) developers often ask, "Why isn't analog mixed-signal
intellectual property (IP) available off the shelf?" The answer
is that analog mixed-signal (AMS) IP is indeed available off the
shelf. More...
- By: Tim Henricks, Cadence Design Systems Inc.
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Technology Showcase
Getting
an algorithm ready for reuse
OA TMS320C6205 provided enough horsepower
to execute the algorithms, but the major challenge was how
to deal with the available 64 kbytes of internal data memory.
Everyone assumes that algorithms written
in C++ are easily portable across platforms. This is not true
in practice. On our first attempt to port the algorithm, we
recompiled the code on Texas Instruments' Code Composer Studio.
But when we ran the code on the DSP, it took five seconds
to execute against the target execution time of 100 milliseconds.
This 50x slowdown was attributed to the algorithm's being
designed for PC processors. To make the algorithm reusable,
the first step was to completely analyze it and identify the
optimization areas.. Read
More..
-By Ketul Patel , eInfochips Ltd
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eInfochips Corner
Client
success stories
eInfochips provided the client with complete
solution in time owing to its expertise on DM642 and video/
image processing technologies. The project involved developing
Video Surveillance System on TI DM642 platform integrating the
software and optimizing it for performance. eInfochips achieved
15 FPS performance, which was more than the expected figures
of 10 FPS. More... |
News
eInfochips Offers VeriSuite
One of the Industry's Most Comprehensive Verification Services
Package and IP Library
VeriSuite
is reusable across a multitude of designs and therefore significantly
reduces development costs and time to verify a chip
More..
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