Having trouble seeing this email? Click here
 
July 2004, Vol I Issue XI
 

  Welcome to the monthly issue of Dashboard, your source for industry news in ASIC & Embedded technology areas, and happenings at eInfochips.

Top Stories of the month
1 Approaches to accelerated HW/SW co-verification
2 Chip architecture allows "testless" design flow
3

Meeting the Challenges of VoIP ATA Designs

4 Practical Approaches to Improving ASIC Verification Efficiency
5 Fuzzy logic does real time on the DSP

Technology Showcase:
Implementing Verification Components on FPGA.Read more..


eInfochips Corner

 
Client Success Story Product Realization: High-end Navigation system with multimedia features
Having complementing skills with the client team, eInfochips’ product design services group offered solution to get the product to the market quickly.
Designer's Corner

Working with Synchronous resets?
Effective HDL coding method for problem free synchronous resets

News

eInfochips’ CEO bags the AMA Outstanding IT Entrepreneur of the Year Award 2004

 

eInfochips is an Integrated Design Services company with over 150 engineers exclusively focused on Electronic Systems Design and Verification.

The company offers products and services with expertise in the areas of ASIC/ SoC design & verification and Embedded Systems development


 



Designer's Corner

Tip of the Month

Implementing Synchronous Resets



 

1. Approaches to accelerated HW/SW co-verification
What if your software was tested and working before first silicon came back from the foundry? What would that do to your product's delivery schedule? As more and more electronic products have extensive software content, designers are faced with serious project delays if they wait for first silicon to begin software debugging. Indeed, "first software" becomes the pacing milestone for product delivery. More..
- By Ray Turner

2. Making the UWB PHY a "Transparent Patient"
The debate about the relative merits of Multiband OFDM and Direct Sequence UWB (DS-UWB) continues unabated. The proponents of each approach praise its particular merits, leaving designers to perform comparative analyses based upon their own definitions of operational requirements. The IEEE has taken the responsibility to bring order into this chaos, but how does it-and the industry as a whole-make a sensible standards decision without solid comparison data? More..
- By Johannes Stahl

3. Meeting the Challenges of VoIP ATA Designs
For VoIP services to continue to grow, carriers need lower-cost phone adapters that are robust and easier to install. But, to make that happen, designers must make some difficult hardware and software decisions. Here's a look at some of the tough choices that must be made.More..
- By Jeff Dionne and Brian Davis

4. Practical Approaches to Improving ASIC Verification Efficiency
Statistics show that software coding, even when done well, has 1 to 3 defects per 100 statements. That's too many errors for any application, let alone for ASIC design, in which undetected errors become embedded in the final product. It's not surprising, therefore, that software verification is a major aspect of ASIC development, accounting for more than half of the end product's labor costs.More..
- By Stuart Riches and Martin Abrahams

5. Fuzzy logic does real time on the DSP
Fuzzy logic doesn't require strange hardware or new programming languages, just a different approach to set membership. Plenty of physical systems, from elevators to boilers, can benefit from fuzzy-logic programming. This article explores progamming a commercial DSP chip to create a basic fuzzy-logic controller. More..
- By Byron Miller

Technology Showcase

Implementing Verification Components on FPGA

With the ever-increasing size and density of ASIC, conventional simulation based verification has become a bottleneck in the project development cycle. As we go towards system level simulation, the debug time increases steadily. The "Synthesizable Verification Components" are a good fit for verification after 90% of the design is mature.- More..


eInfochips Corner
Client Success Story
Our client is a leading European company developing innovative navigation systems.This project involved developing a high-end Navigation System with multimedia features. Having complementing skills with the client team, eInfochips’ product design services group offered solution to the client to get the product to the market quickly.More..
News
eInfochips’ CEO bags the AMA Outstanding IT Entrepreneur of the Year Award 2004
The Jajoo - AMA Centre for Entrepreneurship in IT has instituted this award to recognize enterprising individuals who have built a successful IT organization in Gujarat and have made a significant contribution to the industry with their leadership.More..

Designer's Corner

Synchronous resets are based on the premise that the reset signal will only affect or reset the state of the flip-flop on the active edge of a clock. The reset can be applied to the flip-flop as part of the combinational logic generating the d-input to the flip-flop. If this is the case, the coding style to model the reset should be an if/else priority style with the reset in the if condition and all other combinational logic in the else section. If this style is not strictly observed, two possible problems can occur.- More..


If you have suggestions or feedback, or would like to contribute to our newsletter, please contact us: we would be delighted to hear from you.
To unsubscribe please mail dashboard@einfochips.com with 'remove' in the subject