January 2004, Vol I Issue V

1. Achieving signal integrity for ASICs, PCBs and packages 
Higher speed performance comes at a price: signal integrity becomes a significant portion of the design effort and includes contributions from not only the ASIC, but the package and the printed circuit board (PCB) as well.. More... 
- By David Chase

2. Study eyes pickup in design and EDA
Design activity is likely to pick up in 2004, with a corresponding increase in demand for EDA tools, according to a new study released by RBC Capital Markets. More...
- By Richard Goering

3. Designing high-density voice-capable WLANs
Getting to the sort of user density that large enterprises will expect for pervasive WLAN deployments, and running voice across the same enterprise wireless network, is not easy over traditional systems designed for basic data connectivity. Nonetheless, such a network is possible.  More...
- By Vaduvur Bharghavan

4. How to write DSP device drivers
As digital signal processors pick up peripherals, you'll need to write new device drivers. Here are some time-saving tips for writing them for platforms based on DSPs. More...
- By Nick Lethaby and David Friedland

5. Standardizing Fixed Broadband Wireless
Despite their promise, fixed broadband wireless systems have fallen short in becoming a cost-effective method for delivering voice, video, and data services wirelessly to homes, offices, campuses, and other last-mile applications. More... 
- By William Stallings

eInfochips Corner

Designer's Corner

Improving clock-gating for saving power The gate count of ASICs is increasing drastically while factors such as area, cost & power are decreasing. Nowadays RTL coding is not restricted to front-end design as it used to be and designers are equally concerned with issues such as layout & power consumption. Though Clock Gating is a well-known concept for power saving, for technologies below .18 µm mere switching OFF of the clock is not good enough. For maximum power saving the data toggle also needs to be switched OFF with the clock. While tools such as Power Compiler are smart enough to know which signal is to be used for Clock Gating, they are still not intelligent enough to change the architecture of the RTL code.  Consider the following example, there is an input and depending on the logic it might be required to hold the signal at the output. This can be achieved by using a re-circulating flop to hold the value. If the select line generates a Hold, the signal will only be asserted when it is required to hold the value (by default the input will always be passed to the flop). OR  The same signal can be implemented as Load, which will be generated only when required (by default it will be 0).  If a gating element is added in the flop then the second implementation (Load) will save more power then the first implementation (Hold) since the data input to the flop will only be toggled when required. Example of incorrect code always @ (posedge of clk)    if (ac == 1'b0)       out <= out; // Hold the value if no ack    Else      out <= in ; // Default - always pass the value irrespective of valid command Example of better code  always @ (posedge clk)    If (ack == 1'b0)       out <= out ; // Hold the value if no ack    Else if (valid_req)        out <= in ; // Load only if there is a valid request    Else       out <= IDLE_cmd; // Default - just keep IDLE command

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