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1. Stretch
Goals: Bridging the DSP/FPGA Gap
In embedded system design there is a constant struggle between
having a flexible programmable solution that can vary with changing
market dynamics, and delivering the cost/performance results required
to create a differentiated product. More...
- By Amy Malagamba, FPGA and Programmable
Logic Journal
2. Easing
verification challenges for IP reuse
It was probably no surprise to anyone when the idea of reuse
first started to appear in the development of chips. At first the
industry turned to salvaging, or the reuse of blocks that were never
intended to be reused. Later the ability to buy pre-designed blocks
of functionality from third parties, which could be hooked together
by the system designer, enabled huge chips to be put together in
a fairly short amount of time. More...
- By Brian Bailey
3. Selecting the right media
processor for networked multimedia designs
By taking system-level issues into account at the initial
processor selection stage, designers can ensure that there is a
pathway for necessary upgrades as network and multimedia standards
evolve.The choice of media processor for multimedia applications
is determined by the performance and connectivity requirements of
the design. More...
- By David Katz and Rick Gentile, Analog Devices, Inc.
4. Back
to the basics: implementing DSPs on low-cost FPGAs
In the past, low-end FPGAs were the result of cost-reduced
architectural derivatives of high-end FPGA platforms manufactured
on trailing-edge process geometries. As the penetration of FPGAs
into consumer systems continues, the use model is moving from being
glue/control logic-centric to core data processing-centric, changing
the dynamics of the low-cost model. More...
- By Suhel Dhanani, Xilinx
5. Testing
an FPGA: When Is Enough, Enough?
The FPGA is often in the center of designs performing such
functions as high-speed digital signal processing, complex embedded
processing, or system data aggregation. The ability to feed this
juggernaut of compute power becomes daunting.. More...
- By Brent Przybus, Xilinx
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Technology
Showcase
A design can be considered
testable if a satisfactory set of test patterns is generated,
evaluated, and applied to improve quality and minimize time-to-market.
Therefore, a testable system implies better fault coverage,
a shorter testing time, a higher-quality product, and a shorter
time-to-market. Two tasks must be accomplished in DFT: generating
efficient test patterns with maximum test coverage, and then
verifying test patterns. Afterward, these generated test patterns
are applied to the real design, and timing information is
considered. Read
More...
- By Udhaya Kumar, eInfochips
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eInfochips
Partner Showcase
The path to more effective SOC design
is the multi-processor system-on-chip (MPSOC) design approach.
The MPSOC approach gives designers flexibility to produce
chips that are right the first time (lowering development
cost) and remain right over time (increasing manufacturing
volume and revenue).
Read
More...
- By Chris Rowen, PhD, Tensilica, Inc
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eInfochips Corner
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Customer
Success Story
Verification of Network Co-processor
We defined and developed Module level and System Level Test-plan
Verification environment. This project also included code
coverage analysis, gate level simulation and performance analysis.
More...
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