Our client was a California (USA) based company providing unique system solutions for intelligent broadband arena. Client's system has a state-of-the-art architecture which enables the emerging needs of the data storage business.

Background

Client's chip-set, multi-million gate VLSI devices are targeted for storage area networking (SAN) needs. It provides multiple Giga-bits/second throughput. Along with the best architectures in its field, the client's SoC delivers much needed customer requirements like scalability, portability and comprehensive solutions.

eInfochips’ Role:

eInfochips' role was to provide High Sigma (Zero Defect) quality SoC verification services.

eInfochips played a key role in defining and executing several milestones like:

• Definition and development of comprehensive verification environment
• Development of BFMs for the major interfaces of the SoC
• Development of Traffic Monitors at the various points in the traffic flow
• Generation of quality test scenarios for full chip and system level verification
• Assurance of RTL verification using coverage tools
• Board level physical verification

How was this achieved?

Major verification steps executed at the client site:

• Identification of verification environment based on the architecture and design-specification.
• Defined and developed comprehensive verification suite, using Verilog HDL which includes
  • Bus functional models for major interfaces
  • Inter block monitors to check the data integrity in the traffic flow
  • Partial emulation of the software part of the system
  • Harnessing both in-house and third party blocks
• Based on the design specification, identified and generated set of directed test patterns for full chip and system level DUTs
• Development of random test pattern generator to cover the corner cases of the design
• Application of directed and random test patterns on the RTL Code to verify the design functionality. Debugging of the failed test patterns. Simulators like Verilog-XL, NC-Verilog and VCS have been used during this stage
• Functional coverage has been assured using Cover Meter (Code coverage tool)
• As a part of post layout verification, performed the gate level simulation with SDF file back annotation.
• Also involved in the board level testing to verify the functionality of the system.