Our client based in California, USA provides silicon solutions of high performance packet classification network coprocessors (as an integral part of the network processor fast path) for policy-based network equipment, such as Virtual Private Network (VPN) devices, bandwidth managers (up to OC192c), fast firewalls, service aggregation devices, core switch routers, access routers, Voice over IP (VoIP) devices and network probes, used at the edges of the network.

Introduction to Network Co-processor

Network processors are programmable devices that perform packet processing on per packet basis and provide a flexible hardware platform that can easily and rapidly be provisioned to accommodate ever-evolving standards and protocols. The key to intelligent routers and switches is packet classification done by network co-processors. Packet classification is the function of identifying and categorizing packets of data moving across the network. It is this function that allows network equipment to recognize the application and determine the Quality of Service (QoS) required. This is essential to applications that require real-time delivery of data such as Internet Telephony, audio over IP, video over IP, and those that require security features such as VPNs and Firewalls. Wire-speed, network security, traffic monitoring as well as statistics, encryption/decryption, more than 1 layer classification are the key attributes of Network Co-processor.

eInfochips’ Role:

eInfochips' role was to perform an in-depth qualitative Verification of our client's Network Co-processor that covers the following major attributes:

• Defining Module level and System Level Test-plan
• Development of Verification environment
• Test Vector Development
• Code Coverage Analysis
• Gate Level Simulations
• Performance Analysis

How was this achieved?

• Defined test plans for Module and System level verification
• Developed Bus Functional Models (BFM) and Protocol Checkers (in VERILOG as well as PERL) for various blocks of N/W co-processor
• Generated directed, corner and random test vectors using scripting language
• Implemented Verification environment (in VERILOG as well as PERL) that supports RTL simulation as well as C-reference model simulation
• Carried out grey-box (black-box as well as white-box) verification of Network Co-processor
• Comprehensive Test Bench developed for module and system-level verification
• By performing Code Coverage analysis on modules that resulted as 95% of the code has been hit by different tests
• Gate level simulations have been carried out on the "Synthesized Net list" (gate level representation of RTL code)" as well as on "P & R Net list", which has confirmed that RTL and gate o/p matched every clock cycle
• Chip performance has been measured by calculating latency, throughput and number of searches per second for different configurations of Network co-processor