Application
overview
Our customer is a global leader in semiconductors
for wired and wireless communications. Their products enable the
delivery of voice, video, data and multimedia to and throughout
the home, the office and the mobile environment.
We were involved in tape-out of a flip chip. We implemented customer’s
verilog netlist of a digital video SoC design into a physical layout
of manufacturable hardware. This SoC was implemented using Magma
tool chain on TSMC 0.13u technology. The tape-out was successfully
executed in 14 weeks.
Block Diagram of the Digital Video Chip
Design Complexity
- 8 million gates
- 52 memories
- 28 analog macros
- 1250 IOs
- Flip chip package
- 300 Mhz
- 12 Clock domains
eInfochips’ Role
eInfochips’ physical design team was responsible
for implementing the top level hierarchical netlist to GDSII. The
team was also responsible for implementing the sub blocks from hierarchical
netlist to GDSII. The various stages of our involvement are
- Top Level Floorplanning
- Analog and digital IO pad placement and pin ordering
- Custom routing for clock network, analog modules and flip chip
solder bumps
- Rectilinear shape Floorplan and hierarchical implementation
of sub blocks
- STA and Formal verification at Block level
- SI closure and IR drop analysis at Block level
- Physical verification of sub blocks
- TCL scripting for all of the above activities
Challenges Addressed
- Implementing clock tree synthesis by writing custom scripts
to place buffer tree, clock tree shielding and skew minimization
- Complete Implementation of hierarchical sub blocks using custom
scripts
- Achieving timing requirements, through customization activities
like creating regions, grouping, clustering, data path routing
and multiple Floorplan
- SI closure, Power analysis, formal verification, DRC/ERC/LVS
clean up at block level
Tools Used
For the top level flow Synopsys tool chain was
used, while for the block level flow the Magma tool chain was used.
Benefits:
Our customer benefited from the flawless execution
of the entire project, we leveraged our tools & design flow
expertise ensuring first time silicon success. |
