Our customer was a US based industrial leader in manufacturing physical layer devices, framers, timing technology solutions, and reconfigurable mixed-signal arrays. This project was based on converting a cell library from one grid to another.

The library to be converted comprised of 0.25um custom cells. These cells varied from simple "via chains" to "diodes", "resistors", "capacitors", "pnp junctions" and "FET based" to complex "memory cells" and "ring oscillators". And so the design was digital as well as analog in nature. The cells were mainly pad cells and the functionalities of the structures mentioned above were implemented between pad gaps. Once the design was fit in the geometry, DRC and LVS rules were run to ensure that the design was clean of any violations.

eInfochips’ Role:

• Generating new cells of 50 * 1080 um (standard die size) out of two modules each having approximate dimensions of 90 * 1000 um.
• Shrinking the cells in order to fit them into reduced die size.
• Accommodating the structure in 5um grid to 4 um grid.
• Generating the schematics.
• Running DRC and LVS rules on these shrunk cells using "Calibre DRC and LVS" tools.
• Reducing the hierarchies from cells and running LVL using "Calibre" tool in order to maintain the cell.

How was this achieved?

The prerequisites for this project were good knowledge of layout and the metal layers used in chips with their connectivity.

• Initially the team went through rigorous training of the tool and solved exercises to get acquainted with it.
• The client had strict timelines for finishing the project and so the team started working with simple cells to begin with
• Apart from the technical work, the engineers also had to conform to client's procedures of maintaining the work.
• Initially it was difficult to solve the violations caused due to DRC and LVS runas the tools and environment were new, but the team quickly mastered the tools and started delivering modified clean cells from the second week.
• The project was finished on time with all QA process.

Technical Highlights

• Tools used :- Cadence's Virtuoso Layout Editor with Schematic composer, Cadence's Assura DRC and LVS, Mentor Graphics' Caliber DRC and LVS.
• Platform :- Sun Solaris
• The cells were converted from 0.25 um to 0.18um, 0.13um and 0.10 um.

Conclusion:

More than 250 cells were converted within duration of 3 months. The project was delivered on time with QA processes and support.