The client is a leading developer and global supplier of high-speed VLSI solutions to communications network equipment manufacturers in end-markets viz. the Worldwide public telecommunications network infrastructure, the Internet infrastructure and Wide Area Networks (WANs).

The design consisted of Utopia interface and customized processor interface to data exchanges to other chips and software. The chip works at 133 MHz with 64 bits data bus width. The density of the devices is, 0.1 Million gate Data Context Manager for AAL SAR.

Scope of work

eInfochips' role was to perform core design and in-depth verification of ATM SAR and was involved in:

• Thorough study of ATM SAR and Traffic Manager architecture
• TL coding and synthesis
• Defining module level and system level test-plan
• Development of verification environment
• Test vector development
• Code coverage analysis
• Hardware-Software co-verification

Block Diagram

Technical highlights

• The Packet Express is ATM SAR and Traffic Manager protocol implementation. It has over 0.4 million-gate count. It is working on two different clock domains having frequencies of 133MHz and 150MHz
• It interfaces with Packet Processor (Client Specific Convergence Sub layer) at application layer and UTOPIA at the Physical Layer. It also interfaces with the Management Software
• On the segmentation side, it accepts packets from Packer Processor, converts into the ATM cells and sends ATM cell over the UTOPIA interface with the traffic rate being controlled by the Traffic Management module
• On the reassembly side, it receives ATM cells from UTOPIA, composes packet and forwards it over to Packet Processor. Implementation of SDRAM controller interface for Packet/Cell Storage, on chip DPRAM for frequency domain convergence and on chip SPRAM for Statistic Performance registers
• Synthesis of Packet Express using Synopsis Design Compiler
• The verification environment is developed using the VHDL, C and Hardware-Software CO-verification using client's proprietary tool
• Defined complete verification environment for the Reassembly block of the AAL SAR; highlighting:
• Test plan and the test strategy
• Hardware Software CO-verification using foreign language interface with C and C++
• Incorporating code coverage in the verification environment using Vnavigator from TransEDA
• Verification of state machines that talk with RAM Controller module and the SAR modules and serves as the controller for all the sub-modules of the SAR block asynchronously accessing the memory
• Verification of the exchange of data between the SAR modules and the RAM controller module based on the context
• Verification of pseudo-circular link list of the control structures in the on-chip SPRAM
• Verification of the control data integrity by keeping track of all the client modules that is talking to the Control RAM controller module
• Verification of interfaces to Traffic Manager for the status update of the control Data Structure
• Verification environment consisted of reusable verification modules for Utopia, SAR and Traffic Manager's golden/reference module, test case harness to combine verification components with traffic generator, making sure inter-operability between the verification components
• Achieved 98% code coverage

Methodology

• RTL coding followed the architecture and functional specifications provided by the client
• The RTL design followed client's proprietary reusable methodology for VHDL coding
• Defined test plans for module and system level verification
• Developed architecture of the interoperable, object oriented and layer based modular verification environment. The verification environment is scalable, programmable and reusable for future versions of the application. The verification environment was designed and implemented using VHDL, C and client proprietary tools
• Developed BFM and Protocol Checkers
• The Traffic generator provides directed, directed random and random test vectors
• Performed Code Coverage Analysis to ensure 100% coverage