eInfochips is an Integrated Design Services company with over 150 engineers exclusively focused on Electronics Systems Design and Verification.

The company offers products and services with expertise in the areas of ASIC/SoC design & verification and Embedded Systems development

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eCM: e Conversion Methodology

Legacy codes written in languages such as Verilog/VHDL, C/C++, PERL or any other tool-specific language, converting to a different language may seem difficult. Even still, there are many engineering teams who have successfully made the transition to a verification environment driven by a verification language such as Verisity's e, and have experienced significant benefits. eInfochips believes these long-term benefits far outweigh the one-time investment required for the initial conversion - especially when a thorough conversion methodology is followed throughout the process.

The e Conversion Methodology is a flexible conversion approach that provides the added benefits of reuse. The methodology embraces Verisity's e Reuse Methodology (eRM), resulting in more manageable, layer-based, modular code that can be reused within a project or among projects. When combining the benefits of environment reusability with Specman Elite's coverage-driven verification methodology, the return on investment achieved through code conversion is substantial over multiple projects

- For the various steps of eCM More...

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Taking care of 'x' and 'z' signals during e code development

While checking for signals from the verilog or vhdl variables, allow the necessary conditions for checking x and z states of the signals. For e.g., consider the following code. This code exemplifies the effect of 'z' on the rise events.

extend sys {
simu : simu is instance;
};

unit simu {
keep hdl_path() == "test_sim";
sig_a : string;
keep sig_a == "a";
// signal test_sim.a can assume any of the values from 0,1,x,z

event a_rise is rise('(sig_a)') @sim;
// 1. from '0' to 'z'
// 2. from '0' to '1'
// 3. from 'x' to '1'
// 4. from 'x' to 'z'
on a_rise {
out (">>>>","sig_a rise at ",sys.time, " time");
};
};

The above code will execute and give the rise events as mentioned in points 1 to 4 in the comments.
Changing the code as below will limit the rise event to changing from 'x' to '1' and from '0' to '1'.

event a_r is rise('(sig_a)') @sim;
event a_rise is true('(sig_a)' !== 1'bz) @a_r;

The same can be done for fall events by checking for 'x' values.