October 2003, Vol I Issue II

1. Embedded processors of tomorrow

Goodbye binary arithmetic, instruction sets, and assembly language programming. Hello 4.5-billion transistors, 250GHz processors. O brave new embedded world! More... 
- By Jim Turley, Embedded Systems Programming

2. Revolution comes to SoC methods
The winners in the system-on-chip revolution are winning because they have adopted system-level design tools and methodologies. Leading designers are using these approaches because traditional methodologies cannot deliver the orders-of-magnitude increases in design productivity required to meet modern SoC design challenges More...
- By Tim Herbert, EE Times

3.  Verisity Enhances Customer Productivity With Reusable PCI Express e Verification Component
New e Verification Component (eVC) Accelerates Verification of PCI Express-Based Chips … The PCI Express eVC dramatically shortens the time needed to create a PCI Express-based verification environment  More...

4. Low-priced FPGAs gaining ground
Time-to-market pressures and rising ASIC development costs have helped make low-priced FPGAs an attractive alternative, and suppliers are happily seizing the opportunity More...
- By Christa Souza, EBN news

5. Rethinking How to Handle Backplane Traffic
Proposed backplane architecture separates control and address information from packets on a channel-by-channel basis to improve overall data channel throughput More... 
- By Mike Fowler, Fairchild Semiconductor

eInfochips Corner

Featured Product eInfochips broadens IP offerings with launch of  fully synthesizable, easy-to-use, high-performance PCI2.2 Master-Target soft cores for designers of networking ICs and system devices  More...	Client Success Story eInfochips develops a verification environment that uses state-of-the-art verification techniques & tools, leverages design as well verification IP reuse and can be used to verify multi-million gate SoCs  More...
Product Announcement eInfochips OCP2.0 eVC offers a 10x to 15x productivity increase for verification of designs incorporating Open Core Protocol interfaces. A sneak preview of the eVC datasheet, especially for the Dashboard readers More...	Event Verisity's verification seminars in Bangalore & Hyderabad - Nov'03: eInfochips highlights in case study how to leverage coverage driven verification methodology in real-world designs  More...

Designer's Corner

Extend EDMA capability on C 671x DSPs C6x1x DSPs offer EDMA (Enhanced Direct Memory Access) for highly configurable data transfers. Two of the important features that EDMA offers are Linking and Chaining the data transfers. Linking EDMA channels is a characteristic that allows the application developer to reload the channel configuration parameters for the next transfer. Linking does not trigger the next transfer; it only reloads the new configuration. Chaining EDMA channels is a characteristic that allows the application developer to configure two channels such that the transfer completion event of one channel triggers another channel transfer. Only 4 channels (channel nos. 8,9,10 & 11) out of total 16 EDMA channels on the C671x DSPs are chainable. This can be a limitation in a system where automatic triggering of multiple data transfers is needed in a sequence. Consider that 4 EDMA transfers need to be triggered by a single call. Using 4 EDMA channels out of which 3 are chainable, as shown in the figure below can do this: Chan2 chained to Chan1,  Chan3 chained to Chan2, and  Chan4 chained to Chan3, However, using only 2 chainable EDMA channels and one PaRAM table entry, as shown in the figure and the accompanying code below can also do this: Chan2 is chained to Chan1,  Chan3 chained to Chan2, Chan2 parameters gets reloaded with new configuration parameters in the PaRAM table, and  Chan2 chained to Chan3, // Allocate 2 Parameter RAM tables from the PRAM EDMA_allocTableEx(2, hEdmaRld); // Allocate any EDMA channel. This channel will start the transfers hChan1 = EDMA_open( EDMA_CHA_ANY, EDMA_OPEN_RESET); // Allocate the Transfer Complete Code for the Chainable EDMA channels chan8Tcc = EDMA_intAlloc(8); chan9Tcc = EDMA_intAlloc(9); // Open the 2 Chainable EDMA channels hChan2 = EDMA_open( chan8Tcc, EDMA_OPEN_RESET); hChan3 = EDMA_open( chan9Tcc, EDMA_OPEN_RESET); // Configure all the 4 EDMA channels,  the Cfgx structures are filled already EDMA_config( hChan1, &Cfg1); EDMA_config( hChan2, &Cfg2); EDMA_config( hChan3, &Cfg3); EDMA_config( hEdmaRld[0], &Cfg4); EDMA_config( hEdmaRld[1], &CfgNull); // Setup the links for reload tables  EDMA_link(hChan2, hEdmaRld[0]);  EDMA_link(hEdmaRld[0], hEdmaRld[1]); // Chain the EDMA channels  EDMA_chain(hChan1, hChan2, EDMA_TCC_SET, 0);  EDMA_chain(hChan2, hChan3, EDMA_TCC_SET, 0);  EDMA_chain(hChan3, hChan2, EDMA_TCC_SET, 0); // Enable the Chain the EDMA channels  EDMA_enableChaining(hChan2);  EDMA_enableChaining(hChan3); // This function will start the first EDMA transfer EDMA_setChannel(hChan1);

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