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November 2003, Vol I Issue III

Welcome to the November issue of Dashboard, your source for industry news in the ASIC/ Embedded technology areas and eInfochips.

Top Stories of the month 

1 Structured ASICs allow improved design flow
2 PCI Express and Advanced Switching: different chores
3

Monitoring Data Throughput in Wireless Apps
4 Verisity Addresses Verification Predictability and Resource Utilization with Industry's First Verification Management Solution
5 AMCC, IBM, Infineon Technologies, Texas Instruments and Xilinx Team to Align 10Gbps Standards


Technology Showcase: e Reuse Methodology - The Key to Verification Reuse
 This month's profile: Drawing from over 350 man-years of the collected experience of Verisity’s customers, partners, consulting engineers and internal eVC developers, eRM delivers the best known methods for architecting, coding and packaging e-based verification components (eVCs). More.. 


eInfochips Corner

Featured Product eInfochips' Video Daughterboard (vDB). Compliant to TMS320 cross-platform daughterboard specifications V1.0.  
Client Success Story   eInfochips executes design and verification of ATM SAR and Traffic Manager chip for a leading global provider of high-speed VLSI solutions 
Event Verisity's Verification Seminar (Bangalore): eInfochips highlights Coverage Driven Verification for enhancing verification productivity
Designer's Corner Tip - An unconventional way to program the FLASH in DSP & FPGA based systems
 

 

Face-to-face!

Verisity's Verification Seminar - Bangalore (19th Nov) 
eInfochips presents a case study on CDV methodology in real-world designs


Designer's Corner
Tip of the Month

Unconventional way to program the FLASH  in DSP & FPGA based systems

1. Structured ASICs allow improved design flow

Structured ASICs represent a new ASIC capability that offer a promising alternative to cell-based ASICs for the large mid-volume market. More... 
- By John Gallagher, EEdesign

2. PCI Express and Advanced Switching: different chores
PCI Express and Advanced Switching are envisioned as a two-part solution to a two-part problem. An analysis of interconnect requirements for both chassis and appliance-based communications equipment has shown that customer technical requirements divide broadly into two models. More...
- By Mark Summer, EE Times

3.  Monitoring Data Throughput in Wireless Apps
The lossy nature of a wireless network makes the transfer of data a tricky task, to say the least. To account for this loss, designers need to run detailed throughput tests on the RLP and TCP layers.  More...
 - By Paul Dohrman, Agilent Technologies

4. Verisity Addresses Verification Predictability and Resource Utilization with Industry's First Verification Management Solution
vManager Directs Distributed Verification Activities from Executable Plans to Total Coverage and Closure. More...

5. AMCC, IBM, Infineon Technologies, Texas Instruments and Xilinx Team to Align 10Gbps Standards
Initiative - Dubbed UXPi - to Spearhead Common 10Gbps Physical-Layer Standard. The work of UXPi will complement ongoing and upcoming standardization efforts by other industry bodies such as the Optical Internetworking Forum (OIF). More... 

Technology Showcase

e Reuse Methodology: The Key to Verification Reuse

Verification managers engaged in complex IC development projects are under constant pressure to reduce the time and cost of verification, yet they lack the necessary resources. This article describes how reusable verification components, and an underlying verification reuse methodology are essential elements to verification productivity gains. Verisity’s e Reuse Methodology (eRM™) is used to exemplify many of the key concepts.

As the Premier Verification Alliance partner of Verisity, eInfochips has actively embraced the e Reuse Methodology and now adopts eRM in verification component development and solutions.

- Read the article on eRM More...

eInfochips Corner

Featured Product
eInfochips' Video Daughterboard (vDB) presents a modular approach and provides functions to meet requirements of standard video interfaces compliant to TMS320 cross-platform daughterboard specifications V1.0. 
More...

Client Success Story
eInfochips performed design and verification of an ATM SAR and Traffic Manager chip for a leading European supplier of high-speed VLSI solutions. The project was executed under tight schedules and the team had a 24x7 development environment operating both onsite and at our offshore design center in India.  
More...
Event
Verisity's Verification Seminar (Bangalore), 19th Nov '03: eInfochips highlights Coverage Driven Verification for enhancing verification productivity. More...

Designer's Corner

An unconventional way to program the Flash in DSP & FPGA based systems

In a slave parallel mode configuration for Spartan II FPGA (for example), the FLASH is used for loading the FPGA application code at power ON. This application code in the FLASH can be changed by using another 'read-only' Utility code within the FLASH itself, which can be loaded onto the FPGA using a switch for selection. This read-only FPGA utility code when loaded onto the FPGA has the sole function of taking the changed application code data from the DSP interface to the FPGA and write to the application code region of the FLASH. The figure given below illustrates the functionality. The CPLD provides the address sequence to the FLASH.

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