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1. For
better or for worse, Bluetooth weds UWB
On a conceptual level, the announcement last week that the
Bluetooth Special Interest Group would work with ultrawideband proponents
to make its technology compatible with UWB is a win-win collaboration.
More...
- By Patrick Mannion
2. SoC
processing options
Systems-on-chip with multiple processing elements are an
important part of the design landscape, especially for portable
systems that require the high level of integration and the mixed
data and signal processing that SoC devices offer. But SoC design
involves combining disparate elements -- from programmable functions,
such as general-purpose (usually RISC) microprocessors, DSPs, FPGAs
and accelerators, to fixed-function accelerators. More...
- By Gene Frantz
3. FPGA merger with processors
gathers steam
Programmable-logic vendors increasingly are looking to embedded
processor cores as a way to exploit the higher logic densities and
lower costs coming from Moore's Law scaling. And system-on-chip
(SoC) vendors are beginning to add programmable logic to their designs
as well, offering flexibility to the increasing numbers of customers
dealing with changing standards. More...
- By David Lammers
4. The 'why'
and 'what' of algorithmic synthesis
Algorithmic synthesis helps hardware designers build and
verify hardware more efficiently, giving them better control over
optimization of their design architecture. The starting point of
this flow is a subset of pure C++ that includes a bit-accurate class
library. The code is analyzed, architecturally constrained, and
scheduled to create synthesizeable HDL. More...
- By Bryan Bowyer
5. Extracting
clock signals from high-speed communications
One of the tricks to high-speed communication is embedding the clock
signal within the data. Getting the clock back out and using it
to recover the data requires some careful design. More...
- By Greg Le Cheminant
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Technology Showcase
Design of clock network is a critical
task in high performance circuits. The performance and functionality
of circuits directly depend on the characteristics of the
clock network. The physical realization of the clock tree
network not only constrains the chip design but also directly
impacts the controllability of skew/jitter and power, area.
Read
More..
- By Udhayakumar
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eInfochips
Partner Showcase
Development tools are now advanced
enough to allow any designer to tailor a microprocessor core
for specific application tasks. Processor tailoring creates
processor cores for specialized tasks on SOCs in minutes.a
shockingly short amount of time. Because of this rapid ability
to tailor processors for specific tasks, configurable processors
make excellent, high-performance building blocks for SOC design
and can often be used to quickly create functional blocks
that might otherwise require months of manual labor to create
hand-crafted RTL.
Read
More..
- By Steve Leibson and James Kim
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eInfochips Corner
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Featured
Product
SPI-4.2 e Verification Component
The SPI-4.2 eVC represents the data
link layer and can be used to verify the Physical Layer device
following the SPI 4 P2 protocol. More...
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Customer
Success Story
The project involved
development of a full custom macro using TSMC 90nm technology.
The goal was to develop high speed, low power viterbi decoder
macro using the minimum die area within 6 months. More...
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News
ChipMaestro is a portfolio of domain
expertise, IP and services to support ASIC development in
the consumer electronics, communications and computer peripherals
markets. More...
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Events
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42nd Design Automation Conference
(DAC), Anaheim, California, June 13th -17th, 2005.
Visit us at booth # 740
Read
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