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1. FPGAs
Enabling Consumer Electronics – A Growing Trend
Today low-cost FPGAs are at the forefront of the process
curve with architectures implemented on 90nm process technology.
The relentless march down the process curve, coupled with increasing
yields on larger wafer sizes, has resulted in a dramatic decrease
in FPGA costs. More...
- By Suhel Dhanani, Sr. Manager, Xilinx
2. Revving
video encoding on C64x/DM64x DSPs
To avoid the huge cache-miss penalty and CPU stalling, the
algorithm can be broken into three loops, each of them a separate
module that fits into L1P. Instead of processing a single MB at
a time in each loop, the module processes n macroblocks-an MB strip.
More...
- By Cheng Peng, Texas Instruments
3. Inside DSP on Digital
Video: Developing Software for a Digital Video Product
Software development for video applications presents many
of the same challenges as those found in other embedded signal processing
applications. High computational demands coupled with a need to
keep costs low in consumer products often mean that aggressive software
optimization is required. More...
- By Amit Shoham, BDTI
4. Trust
designs, but verify, say panelists
Successful IC verification cannot be relegated to second
fiddle in the design orchestra. Not only independent independent
design and verification teams are required, but also a concurrent
design and verification development environment. More...
- By Nicolas Mokhoff, EETimes
5. 90nm
Custom SoC? Not That Hard When Most of It's Already Working
One of the tricks to high-speed communication is embedding
the clock signal within the data. Getting the clock back out and
using it to recover the data requires some careful design. More...
- By Steve Williams, SoC Business Development, Toshiba America Electronic
Components, Inc.
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Technology Showcase
Layered BSP development task
can be divided into high level and low-level development.
By providing a practically stable upper layer, Windows® CE
BSP development often is limited to low level OAL development.
Read
More..
- By Harshvardhan Bokil
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eInfochips
Partner Showcase
The enhanced instruction set includes
16-bit operations to reduce code size by 20% to 30%. In addition,
TI claims the C6455 is the first DSP chip to pack both Serial
RapidIO links and a 1-Gbit Ethernet media access controller.
Read
More..
- By Dave Bursky
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eInfochips Corner
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Featured
Product
Image Resize Design IP Core
IMR (Image Resizing) IP core provides
facility to shrink or enlarge images according to user requirement.
It implements nearest neighbor method for image enlargement
and interpolation method for image shrinking. More...
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Customer
Success Story
Behavioral model development of
DDR IO Cell
eInfochips role was to develop a Verilog behavioral model
for DDR IO Cell defining the cell micro architecture, developing
and supporting intergration with customer environment. More...
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News
eInfochips to double headcount: Expand
presence to tap markets in Europe and Asia . More...
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