| |
1. Billions
of transistors, and Moore
The nanoelectronic-IC era will enable chips with, literally,
billions of transistors, presenters said. But with the market's
once-predict-able double-digit growth rates no longer assured, the
industry is struggling to identify applications of nanoelectronics
that will fill its fabrication facilities and give a return on its
massive investments. More...
- By Stephan Ohr, Nicolas Mokhoff, Ron
Wilson, EE Times.
2.
Verification requires new methodologies, panelists say
There's no silver bullet that can solve the design verification
problem. There are tools that can help, but the real issue is rethinking
the methodology. More...
-By Richard Goering, EE Times.
3. Leveraging structured
ASICs for signal processing applications
Hardware tasks, traditionally partitioned between the ASIC
and FPGA, now primarily fall to FPGAs, which provide a cost-effective
alternative for DSP implementation that easily can be adopted for
a broad range of applications. More...
-By Brian Jentz, DSP Marketing Manager, Altera
4. Prime-time
Processing Are Embedded Systems on FPGA Ready?
Over the coming months, watch for an increased pace of new
tool and technology announcements, lower price points for system-on-chip
capable FPGAs, and increased variety and diversity in offerings
of processors, peripherals, and embedded platform support. More...
-By Kevin Morris, FPGA and Programmable Logic Journal.
5.
The Real Challenge of System-Level Design
The main challenge System-Level Design (SLD) tools have to addressis
bridging the gap from specification to implementation and reducing
the guessing as much as possible. More...
- By Vincent Perrier, Co-Founder and Director of CoFluent Design.
|
Technology Showcase
Reference designs and flows
are coming on the RF side and third-party verification IP
is accumulating on the protocol side, sure indications that
early designs are going on somewhere. UWB is moving out of
the realm of papers and standards reviews, and toward early
silicon.
Read
More..
-Ron Wilson, EE Times
|
|
eInfochips Partner
Showcase
Employing a robust, highly
scalable coverage engine is a significant step toward multiplying
your productivity. The next step introduces a coverage analysis
solution that allows your engineering team to leverage data
in a metric-driven verification process. Read
More..
-By Moshe Gavrielov, CEO,Verisity
|
eInfochips Corner
|
Client Sucess
Story
Verification of OC-192 line card
framer chips
Our customer is a US based company,
an established world leader in design and manufacturing of
communication infrastructure. This product will be used for
broadband services to fine-tune the bandwidth allocation to
customers without service outage resulting in lower costs.
More...
|
News
eInfochips unveils digital multimedia platform
ASIC design and verification services provider eInfochips
has introduced what it claims is the industry's lowest cost,
high-performance video and imaging development platform for
digital multimedia applications.
More..
eInfochips
receives CII Award for "Emerging Info. Comm. Technology Enterprise
for the year 2004"
eInfochips
was awarded the "CII Emerging ICT Enterprise Award" at the
Communication and Information Technology Conference, 2005.
More..
|
|
Featured
Product
SPI 5 Design IP Core
SPI 5 core is a customized bridge solution for Link Layer
and PHY Layer device based packet interface. SPI 5 core is
used for communication system applications based on point-to-point
protocol. More..
|
If you have suggestions or feedback,
or would like to contribute to our newsletter, please contact us:
we would be delighted to hear from you.
To unsubscribe email us at: dashboard@einfochips.com
with 'remove' in the subject |
